Central synthesizer naming#652
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mkorbel1
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I haven't finished reading it all yet, but first pass a few questions
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This is looking pretty good, thank you for refactoring it this way, I can see how it helps your other upcoming changes!
…al/instance naming routine names
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Looking close now to mergeable!
Clarify comment Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
This aligns central_naming with the simplified naming approach already adopted by all downstream branches (module_services, netlist, source_debug, systemc_trace, fst-writer). Changes: - Remove Namer._instanceNames cache field - Remove Namer.instanceNameOf(Module) method - Update synthesizers to use Namer.allocateName(String) directly - Remove destination tracking from _BusSubsetForStructSlice Benefit: Eliminates duplication across 5+ branches, making each branch truly orthogonal and mergeable without conflicts. Trade-off: Instance names no longer cached across synthesis passes, but all downstreams already use this simpler approach.
# Conflicts: # tool/gh_codespaces/install_dart.sh
instanceNameOf(Module) allocates a collision-free instance name on the first call and returns the cached result thereafter. The _instanceNames Map is keyed by Module.instanceNameKey so repeated synthesis passes over the same hierarchy always produce stable names. This method belongs in central_naming because it is pure naming infrastructure with no dependency on any feature branch.
- Update comment: 'allocateName' → 'instanceNameOf' - Add 'submodule instance names are stable across repeated definitions' test (the canonical 'run synthesis twice, same names' regression test) Both belong here since they directly exercise Namer.instanceNameOf, which is now defined in central_naming.
SynthSubModuleInstantiation.pickName was calling namer.allocateName() directly, bypassing the _instanceNames cache in Namer.instanceNameOf. This caused the second SynthModuleDefinition build over the same module hierarchy to see 'inner' already taken and allocate 'inner_0' instead. Fix: call namer.instanceNameOf(module) which caches on first allocation and returns the same name on subsequent synthesis passes.
Two new tests in 'shared instance and signal namespace': 1. 'instance name wins the shared namespace; signal gets the suffix' Asserts deterministic ordering: non-reserved instances are picked before non-reserved signals, so the instance keeps the bare name and the colliding signal is uniquified to inner_0. 2. 'instance-signal collision resolution is stable across repeated synthesis passes' Calls generateSynth() twice and verifies the module body is identical (timestamp stripped). Guards against name drift where the second pass would assign different suffixes.
| /// | ||
| /// Used as the [instanceNameKey] so that, although a fresh | ||
| /// [_BusSubsetForStructSlice] is created on every synthesis pass, its | ||
| /// canonical instance name is memoized against the persistent destination |
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This comment looks like it used to apply to some field but is now just floating around? Should this just be deleted?
| /// Signal names are read from [Namer.signalNameOf] for user-created | ||
| /// [Logic] objects) or kept as literal constants and are allocated from | ||
| /// [Namer.signalNameOf]. Submodule instance names are allocated | ||
| /// from [Namer.allocateName]. All names share a single |
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it actually seems to be using instanceNameOf now? In general, though, I don't think lower-level implementation details need to be enumerated in this comment anyways?
| /// | ||
| /// When [reserved] is `true`, the exact [baseName] (after sanitization) | ||
| /// is claimed without modification; an exception is thrown if it collides. | ||
| String allocateName(String baseName, {bool reserved = false}) => |
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why is this wrapper around getUniqueName present? why not just call the uniquifier's function as we did for signal names?
| /// Delegates to signal namer which handles constant value naming, priority | ||
| /// selection, and uniquification via the module's shared namespace. | ||
| String _findName() => | ||
| parentSynthModuleDefinition.module.namer.signalNameOfBest( |
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Important question: In general for name selection for instances and signals, the order of selection seems very important. For this PR, everything seems clean to me since the order of name selection will be consistent between SystemVerilog generation (as proven in your unit tests). However, I'm curious about the long-term utility of this naming approach when other things start also needing to select names. For example, if you attach debug infrastructure to query what names instances/signals have prior to running the SynthBuilder stack, wouldn't that affect name selection and thus give you different SystemVerilog depending on whether you debugged beforehand or not?
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The debug infrastructure has to run the netlist synthesizer to retrieve names, so by necessity, the Namer has run and assigned canonical names.
| /// The first call for a given [logic] allocates a collision-free name | ||
| /// via the underlying [Uniquifier]. Subsequent calls return the cached | ||
| /// result in O(1). | ||
| String signalNameOf(Logic logic) { |
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this function doesn't seem to be used outside of this class anymore except for in tests and comments? generally the API is replaced by signalNameOfBest? so maybe this should be @visibleForTesting so we don't accidentally use this function elsewhere in the codebase and bypass the correct API?
| /// return a stable identity — typically the [Logic] they drive — so their | ||
| /// instance name does not drift run-to-run. | ||
| @internal | ||
| Object get instanceNameKey => this; |
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Is this thing still used?
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Description & Motivation
Migrate synthesis naming to a central namer so that all synthesizers (and even WaveDumper) can agree on signal naming.
This is needed for a new synthesizer to be added (netlist).
Related Issue(s)
None.
Testing
I ran existing examples in ROHD and compared SV.
I added extensive test matrix
test/naming_cases_test.dartfor the combinations of naming options (reserved, mergeable, etc) for which I generated tests that pass before and after the central naming.Two bugs were filed: bug #648 and bug #649 which are fixed in PR # 650 for the traditional SV code as well as in this PR for central naming).
I ran a very, very, very large design example and compared SV before and after.
Backwards-compatibility
Naming is slightly different due to ordering, so when we do have collisions, we will see _0, _1 on different signals. Plus the two bug fixes involving unnamed substructures and repeated const names.
Documentation
No. None needed.