silk/arm/NSQ_del_dec_neon_intr.c — Multiple optimizations

[rl123567]

silk/arm/NSQ_del_dec_neon_intr.c — Multiple optimizations

• LPC prediction: Replace 16 individual vld1q_s32 loads with ldp (load-pair) inline assembly, loading 8 data vectors + 2 coefficient vectors per block. Use vqdmulhq_laneq_s32 to index directly into 128-bit coefficient vectors, eliminating vget_low/high_s32 split overhead.
• Allpass sections: Fully unroll the allpass loop via macro with compile-time branching on shapingLPCOrder, enabling precise register allocation and removing loop overhead.
• Common subexpression elimination: Precompute Tilt_Q14_Q16 and LF_shp_Q14_Q15 outside the per-sample loop; cache LF_AR_Q14 to avoid redundant vector loads.
• AR_shp_Q28 widening: Remove the scalar tail loop since MAX_SHAPE_LPC_ORDER (24) is exactly divisible by 8.
• State replacement copy: Unroll the numOthers copy loop 16× with __builtin_prefetch to hide memory latency during the candidate state swap.