HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.

Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture

A simple cpu simulator and an analyisis of its performance.

Implementation of a Superscalar CPU with Dynamic Scheduling which support RISC-V standard ISA with standard 'M' Extention

An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.

ECE552: Computer Architecture — Fall 2020.

Instructions Per Count (IPC) Study on 9-Stage Supescalar Pipeline with Out-of-Order Execution

This repository contains code for a Verilog program that simulates a pipelined RISC-V processor with full data bypassing and an integrated iterative multiplier/divider/remained unit for mul/div/rem operations.

Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay

Replay-stable SMT-VLIW instruction-set emulator/runtime with streaming-vector transport, typed-slot scheduling, runtime-owned legality, replay evidence, and compiler/runtime structural agreement.

Simulator of pipelined, superscalar processor core based on RISC-V ISA