🖥️ Explore 20 hands-on experiments to master RISC-V computer architecture concepts using the Ripes simulator for effective learning.

📟 RISC-V (RV32I) assembly programs from Computer Organization & Architecture (COA) lab sessions — covering arithmetic, branching, memory access, loops, and array handling.

This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.

A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

RISC-V 32-bit Assembly project focused on sprite rendering and movement using memory-mapped I/O on an LED Matrix, developed with the Ripes simulator.

Low-level programming and computer architecture research. RISC-V Assembly, Ripes simulations, and hardware-software interaction. Collaboration with Nikita Bulkin (University teammate)

RISC-V assembly with Ripes — tests, pipeline/CPI analysis, forwarding, caches, RGB888→RGB565.

A CPU Simulator

Colección de desafíos de bajo nivel en RISC-V enfocados en eficiencia y arquitectura de procesadores.

Prácticas de la asignatura de estructura de computadores de la Universidad Nebrija

RISC-V 32-bit assembly project that renders a full 256×240 NES-style background using memory-mapped framebuffer in Ripes.