Basic arch path#1
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siddhpant
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Jul 9, 2026
| logic addr_valid; | ||
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| assign word_addr = addr_i[ADDR_WIDTH+1:2]; // Byte to word address | ||
| assign addr_valid = (addr_i[31:ADDR_WIDTH+2] == 0); // Check upper bits are 0 |
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Alignment check missing: addr_i[1:0] == 2'b00
| wire [11:0] imm = IR[31:20]; | ||
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| wire [6:0] imm_11_5 = IR[31:25]; | ||
| wire [4:0] imm_4_0 = IR[11:7]; |
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Same as rd. Let's make naming more explicit about instr type.
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Actually should we even be concerned about decoding here instead of the decoder module?
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| typedef enum logic [0:1] { FETCH, EXECUTE } exec_state; | ||
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| exec_state current_state = FETCH; |
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lets also define PC while at it
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Add supporting file for the 2 cycle RV32I Core.
There was a change of plans. After a quick discussion with team members.
We have decided to change course a simple RV32I architecture.