Enable SPEL powercap driver#1190
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Add CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF. These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Link: https://lore.kernel.org/all/20260318-add-coresight-dt-nodes-for-glymur-v2-1-d76e08f21fa5@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Describe PCIe3a controller and PHY. Also add required system resources like regulators, clocks, interrupts and registers configuration for PCIe3a. Link: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260313-v04-add-driver-for-ec-v4-3-ca9d0efd62aa@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…r PCIe PHY on Glymur Add refgen and qref power supplies in each pcie phy devicetree node. For some instance, refgen and qref may share LDOs with phy LDOs, so add additional power supplies. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Switch opp entry for dispcc to turbo Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…CP on Glymur DT Add remoteproc PAS loader for SoCCP on Glymur DT Link: https://lore.kernel.org/all/20260403-glymur-soccp-v3-1-f0e8d57f11ba@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add iris video codec to glymur SoC, which comes with significantly different powering up sequence than previous platforms, thus different clocks and resets. Link: https://lore.kernel.org/all/20260428-glymur-v3-12-8f28930f47d3@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Add PSCI SYSTEM_RESET2 reboot-modes for glymur to be invoked by the psci reboot-mode driver. The following modes are defined: - edl: reboot into emergency download mode for image loading via the Firehose protocol. Support for these modes is dependent on the psci firmware Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Removing Qdss Dsp node to fix Mahua bootup Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…ngs dependency Removed the glymur-iris.h dt-bindings dependency. Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Removing iommu-map for iris video Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
…ch capable Like USB SS0, the USB SS1 and SS2 controllers on Glymur also support USB role switching. Describe this by adding the 'usb-role-switch' property to both controllers. Fixes: 4eee57d ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-1-409e1a257f1f@oss.qualcomm.com
… SS0 and SS1 The two USB Type-C ports on Glymur CRD are dual-role capable. Do not force their controllers into host mode. Drop the explicit 'dr_mode = "host"' properties so they can use their default OTG mode instead. Fixes: c8b6302 ("arm64: dts: qcom: glymur-crd: Enable USB support") Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Q6APM SID fixed Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Glymur has a True Random Number Generator, add the node with the correct compatible set. Link: https://lore.kernel.org/all/20260424-glymur_trng_enablement-v2-2-0603cbe68440@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
On almost all Qualcomm platforms, including Glymur, there is a Crypto engine IP block to which the CPU can off-load cryptographic computations for achieving acceleration. The engine is also DMA capable due to the presence of an associated Bus Access Manager (BAM) module. Describe the Crypto engine and its BAM. Link: https://lore.kernel.org/all/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.com/ Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
On Qualcomm Glymur SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Enable the nodes required to get QCOM SCMI Generic Extension protocol to probe on Glymur and Mahua SoCs. Link: https://lore.kernel.org/lkml/20260507062237.78051-8-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Add support for camera clock controller for camera clients to be able to request for camera clocks on Glymur SoC's. Link: https://lore.kernel.org/r/20260429-glymur_camcc-v2-3-0c3fd1977869@oss.qualcomm.com Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reset gpio added to touchscreen Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
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The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems for glymur. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://patch.msgid.link/20260519-qcom_spel_driver_upstream-v1-3-75356d1b7f94@oss.qualcomm.com
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The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems for glymur.