Bump ACE repository to latest version#13
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* The original FSM is now split across three modules: decoder, memory_unit and snoop_unit. * The top level design is now identified as ccu_ctrl * Legacy parameter is used to simulate a blocking behavior
* Rework the memory unit to use AXI channels parallelism * Use AXI FIFO to buffer memory transactions * Several bug fixes * Remove Legacy support
* Checks are currently performed by stalling requests targeted at the same set
* Stall the decoder W/R requests if the respective queue is full * Collision now happens on equal tags
* Add one ID bit on the memory side * Add W FIFO to decouple Ax controller and W channel
* Use req/gnt protocol * Serve request in the same cycle if possible
Rework the design to reduce latency
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This PR contains the version of the interconnect presented at the RISC-V summit. Some additiona polishing is needed before merging.