[chip, I2C, DV] Top level I2C host test#473
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Refer to the note about why |
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@marnovandermaas suggested to skip verilator and FPGA images for |
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Generally looking decent to me. I have a few comments on making the SW test a bit clearer and in keeping with other tests
martin-velay
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| uvm_config_db#(virtual clk_rst_if)::set(null, "*", "sys_clk_if", sys_clk_if); | ||
| uvm_config_db#(virtual uart_if)::set(null, "*.env.m_uart_agent*", "vif", uart_if); | ||
| uvm_config_db#(virtual pins_if #(NUM_GPIOS))::set(null, "*.env", "gpio_vif", gpio_pins_if); | ||
| uvm_config_db#(virtual i2c_if)::set(null, "*.env.m_i2c_agent", "vif", i2c_if); |
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Probably best to add a wildcard as if a sub-component of i2c agent tries to get this handle it will fail. But it doesn't hurt us to give this possibility in case:
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| uvm_config_db#(virtual i2c_if)::set(null, "*.env.m_i2c_agent", "vif", i2c_if); | |
| uvm_config_db#(virtual i2c_if)::set(null, "*.env.m_i2c_agent*", "vif", i2c_if); |
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engdoreis
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ziuziakowska
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SW comments addressed |
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I've created #605 to address comments from @martin-velay and @elliotb-lowrisc on |
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Controller writes multiple bytes to the target's receiver and then reads multiple bytes from the same address. At the end of both read and write transfer, the test checks if the transfer was succesful. If yes, then the test compares all the read bytes with the data bytes that was sent as part of write transfer. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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I've run the latest changes locally and found the new test passes with multiple seeds and the changes don't seem to break any other UVM top-level tests.
I did spot one typo, but it's not worth holding back this PR over
This vseq: ** reads the SW symbols to get the timing values ** calculates relevant timing parameter use by the agent to send Ack, Nack and Rdata. ** start the reactive sequence Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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Commands to test:
dvsim hw/top_chip/dv/top_chip_sim_cfg.hjson -i i2c_host_tx_rx -t xcelium -fs 1dvsim hw/top_chip/dv/top_chip_sim_cfg.hjson -i i2c_host_tx_rx_cheri -t xcelium -fs 1Close #507