Message passing 2#8
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Pin Verilator (v5.048) and build it from source into the build tree, then find_package it so verilate() is available - self-contained like fmt and Catch2. Requires host tools autoconf, flex and bison. Also link fmt::fmt into the hextb target, which was missing.
find_package(verilator >= VERILATOR_MIN_VERSION) first; only fetch and build VERILATOR_GIT_TAG (v5.048) from source when no suitable system install exists. Build just verilator_exe and install without man pages so help2man is not required, and clear a stale cached VERILATOR_BIN so the fetched binary is used.
Add OPR IN/OUT to opr_opcode_t, NUM_LINKS/NUM_CORES/SLOT_W/CID_W params, and data_flit_t/ack_flit_t (+ core_id_t/slot_t) for the routed message- passing fabric.
Supports the local cmake (3.20+) while keeping 3.28 policy behaviour, and removes the need for an uncommitted local version override.
Processor decodes OPR IN/OUT, hands the slot/areg to a link interface and stalls (freezes all state) until the rendezvous completes; IN writes the received word into areg. New core.sv wraps processor + private memory + link_interface and exposes the syscall, route-config and DATA/ACK network ports. Single-core hex.sv ties the link ports off (no channels). core_tb drives a tiny OUT program and checks the emitted flit, the stall, and the unblock on ACK.
jameshanlon
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network_top.sv instantiates NUM_CORES cores plus a DATA and an ACK router, wires core k to router port k, and decodes a per-core route-table config port. Lint-verified under Verilator; wired into the testbench next. hexcontainer.hpp factors the HEXN container parsing into a shared header for the testbench (and available to hexsim).
hextb now drives network_top: loads each container image into its core, programs the per-core route tables from the wiring edges, services per-core syscalls, terminates on first EXIT once all active cores exit, and detects deadlock after a sustained no-progress stretch (channel rendezvous freezes PCs transiently). Single images load into core 0 with the rest held in a halt loop.
Compile pipe.x to a network container and assert it prints P on the C++ simulator, and (under Verilator) that the RTL produces the same result.
pingpong.x: two processors exchange a value (bidirectional channels). ring.x: a token ring of three processors reusing a forwarder proc. Both run on hexsim and the RTL (golden cross-checks in tests.py) and as unit tests. Also restore proper '|' line comments on the examples.
- hextb: fix HALT_LOOP to a true self-loop (NFIX F; BR E) instead of escaping after one iteration; capture the FIRST exit code, not the last; parse the container once (load returns it) instead of re-reading it for the edges; static_assert NUM_CORES==4 to guard the hand-enumerated coreOf. - hexsim: use the shared hexcontainer::read in loadNetwork instead of a duplicate inline parser (cannot drift from hextb now). - tests/rtl: factor the duplicated flit bit-layout accessors into flit_layout.hpp, shared by liu_tb and core_tb. - tests.py: compile each message-passing program once and run the same container on hexsim and the RTL (true cross-check), not recompiled. - CMakeLists: check the Verilator configure/make/install results separately for accurate failure messages.
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