Add channel communication (ISA and sim)#7
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Refactor Processor::run() into a step() method returning a StepResult (RUNNING/HALTED/BLOCKED) and extract image loading into loadFromStream(). Add a Channel type and per-processor link slots, and implement OPR IN/OUT as a synchronous point-to-point rendezvous: the second party to arrive transfers one word and unblocks the parked partner; a blocked operation does not advance the PC. Add a System class that loads a network container (magic HEXN, wiring edges, embedded per-processor images), boots all processors, and steps them round-robin until they all halt. Records the first processor's exit code, detects deadlock when no processor can proceed, and backstops the 4-link limit with an unwired-slot runtime error. A plain single image still loads via a fallback path.
Add ChanDecl and ChanFormal AST nodes (parsed as global/local decls and formal parameters), register them as CHAN symbols in CreateSymbols so channel references resolve, and print them in the AST printer. Also adds the visitor scaffolding for the par/in/out statement nodes that follow. Update token_error_unexpected_char to use '@' since '?' is now a valid token.
Add a ParStatement AST node holding a list of branch statements, each of
which must be a procedure call (rejected with a clear error otherwise),
printed by the AST printer. par { p() q() ... } composes one process per
branch.
Add OutStatement (channel ! expr) and InStatement (channel ? lvalue) AST nodes, parsed in statement position after an identifier element, and printed by the AST printer. Includes a reused-worker ring tree test exercising chan/par/!/? together.
Treat a chan formal as a one-word val parameter (the link slot index) in FormalLocations, and generate OPR OUT for c ! e (value in areg, slot in breg) and OPR IN for c ? target (slot in breg, received word stored to a variable or array element).
Add the X compiler back-end for message passing. A program whose main is a top-level par compiles to a network container instead of a single image: - network::analyseNetwork builds the static process graph from main's par (one processor per branch), assigns each processor's channels to link slots in argument order, and validates endpoint counts, writer/reader direction and the 4-link limit (NetworkError). - Each processor image is produced by re-parsing the source and replacing main with a call to the branch's entry proc passing its slot indices as constants, then running the existing single-core pipeline. chan formals compile as val parameters, so proc bodies stay generic and reusable. - hexasm::CodeGen::emitImage emits a full image (size word + program + debug) to a stream so images can be embedded in the container. - The container is loaded and run by hexsim::System; xrun and the unit test harness run via System (single images use the loader fallback). Adds tests/x/pipe.x and end-to-end tests covering a pipeline, a relay chain, runtime deadlock detection and the network validation errors.
hexsim now runs via System, which hardcoded sign-extended char inputs. xhexb.x relies on truncated chars, so EOF read back as 0xFFFFFFFF instead of 0xFF and was reported as an illegal character (breaking tests.py:test_x_compiler_sim). Make System::setTruncateInputs configurable, defaulting to true (matching the hardware/xhexb); TestContext opts into sign-extension for its negative-value tests.
par { a(); b(); c() } now separates branches with ; like the other { }
blocks, by reusing parseStatements. Updates the tests and pipe.x.
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