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Each example comes with C/C++ source code, testbench, a README, and Tcl/Python scripts and/or config file. The examples are organized in categories denoted by the directory names:
| Category | Description | Key Examples |
|---|---|---|
| DSP | Shows DSP Intrinsic Library and Vivado LogiCore FFT and FIR usage in Vitis HLS. | DSP_Intrinsic_Library fft fir/decimator |
| Array | Show how to partition memory arrays. | array_partition_complete array_partition_block_cyclic |
| Interface | Common examples for interface protocols. | using_axi_master using_axi_lite_with_user_defined_offset using_axi_stream_with_side_channel_data |
| Modeling | The essentials for loops, arbitrary precision types and vectors. Condtional control of HLS Pragmas. | variable_bound_loops using_arbitrary_precision_arith using_vectors using_array_stencil_1d conditional_control_of_pragmas |
| Pipelining | Illustrating one of the most fundamental concept of HLS. | hier_func pipelined_loop |
| Task_Level_Parallelism | Dataflow and free running streams with hls::task. Autorestart support in testbench. |
using_stream_of_blocks autorestart unique_task_regions using_directio_hs_in_tasks |
| Misc | Other examples such as the RTL blackbox flow. | rtl_as_blackbox |
| Migration | Examples covering scripted and command-line migration flows to Vitis Unified IDE. | tcl_scripts python_scripts vitis_unified_cli |
| Script Type | Command | Notes |
|---|---|---|
| Tcl | vitis-run --mode hls --tcl run_hls.tcl |
Open the directory containing run_hls.tcl as workspace after running the Tcl script to open in Vitis Unified IDE |
| Python | vitis -s run.py |
Open the created directory w as workspace after running the python script to open in Vitis Unified IDE |
By default C Simulation, C Synthesis and Co-Simulation are run with both Tcl and Python scripts. Modify respective script to run Implementation and Packaging.
Vitis High-Level Synthesis User Guide (UG1399)
Vitis High-Level Synthesis - Useful Resources
Parallel Programming for FPGAs
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