From 49f2e36c98274569e8405640a159eed4ad2eeb1d Mon Sep 17 00:00:00 2001
From: Robin Jadoul <robin.jadoul@3milabs.tech>
Date: Wed, 3 Jun 2026 16:04:31 +0200
Subject: [PATCH 1/2] Add extra constraints to prevent register side effects in
 CPU32 padding rows

---
 spec/cpu32.typ      |  1 +
 spec/src/cpu32.toml | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/spec/cpu32.typ b/spec/cpu32.typ
index e5e8963bc..1c4b3ba85 100644
--- a/spec/cpu32.typ
+++ b/spec/cpu32.typ
@@ -45,6 +45,7 @@ provide these below.
 
 Most constraints correspond to those already present in the CPU, and we present them here first,
 including some updates to the range checking corresponding to the differing types.
+We also need to make sure that for padding rows ($mu = 1$), no side effects can occur.
 
 #render_constraint_table(chip, config, groups: ("decode", "range", "alu", "mem", "logup"))
 
diff --git a/spec/src/cpu32.toml b/spec/src/cpu32.toml
index f26ce0e8c..4983b2527 100644
--- a/spec/src/cpu32.toml
+++ b/spec/src/cpu32.toml
@@ -284,6 +284,11 @@ input = [["idx", "res", "i"]]
 multiplicity = "μ"
 iter = ["i", 0, 3]
 
+[[constraints.range]]
+kind = "template"
+tag = "IS_BIT"
+input = ["μ"]
+
 
 [[constraint_groups]]
 name = "alu"
@@ -350,6 +355,21 @@ multiplicity = "write_register"
 [[constraint_groups]]
 name = "logup"
 
+[[constraints.logup]]
+kind = "arith"
+constraint = "$#`!μ` => #`read_register1 = 0`$"
+poly = ["*", ["not", "μ"], "read_register1"]
+
+[[constraints.logup]]
+kind = "arith"
+constraint = "$#`!μ` => #`read_register2 = 0`$"
+poly = ["*", ["not", "μ"], "read_register2"]
+
+[[constraints.logup]]
+kind = "arith"
+constraint = "$#`!μ` => #`write_register = 0`$"
+poly = ["*", ["not", "μ"], "write_register"]
+
 [[constraints.logup]]
 kind = "interaction"
 tag = "CPU32"

From 943c2aa517b2a7b73e6857b4765bbaafae544ec4 Mon Sep 17 00:00:00 2001
From: Robin Jadoul <robin.jadoul@3milabs.tech>
Date: Wed, 3 Jun 2026 16:14:35 +0200
Subject: [PATCH 2/2] fixes

---
 spec/cpu32.typ      | 2 +-
 spec/src/cpu32.toml | 5 -----
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/spec/cpu32.typ b/spec/cpu32.typ
index 1c4b3ba85..a3c639cc7 100644
--- a/spec/cpu32.typ
+++ b/spec/cpu32.typ
@@ -45,7 +45,7 @@ provide these below.
 
 Most constraints correspond to those already present in the CPU, and we present them here first,
 including some updates to the range checking corresponding to the differing types.
-We also need to make sure that for padding rows ($mu = 1$), no side effects can occur.
+We also need to make sure that for padding rows ($mu = 0$), no side effects can occur.
 
 #render_constraint_table(chip, config, groups: ("decode", "range", "alu", "mem", "logup"))
 
diff --git a/spec/src/cpu32.toml b/spec/src/cpu32.toml
index 4983b2527..72386685e 100644
--- a/spec/src/cpu32.toml
+++ b/spec/src/cpu32.toml
@@ -284,11 +284,6 @@ input = [["idx", "res", "i"]]
 multiplicity = "μ"
 iter = ["i", 0, 3]
 
-[[constraints.range]]
-kind = "template"
-tag = "IS_BIT"
-input = ["μ"]
-
 
 [[constraint_groups]]
 name = "alu"