From 36301072d654cbef89499d9fa907ae008c6efe6a Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Wed, 20 May 2026 18:33:45 -0700 Subject: [PATCH 01/15] basic setup --- platform/dev-mec1723/.cargo/config.toml | 21 + platform/dev-mec1723/Cargo.lock | 1569 +++++++++++++++++ platform/dev-mec1723/Cargo.toml | 79 + platform/dev-mec1723/build.rs | 21 + .../dev-mec1723/dev-mec1723.code-workspace | 23 + platform/dev-mec1723/memory.x | 12 + platform/dev-mec1723/src/board.rs | 45 + platform/dev-mec1723/src/clocks.rs | 56 + platform/dev-mec1723/src/main.rs | 39 + platform/dev-mec1723/supply-chain/audits.toml | 79 + platform/dev-mec1723/supply-chain/config.toml | 358 ++++ .../dev-mec1723/supply-chain/imports.lock | 869 +++++++++ 12 files changed, 3171 insertions(+) create mode 100644 platform/dev-mec1723/.cargo/config.toml create mode 100644 platform/dev-mec1723/Cargo.lock create mode 100644 platform/dev-mec1723/Cargo.toml create mode 100644 platform/dev-mec1723/build.rs create mode 100644 platform/dev-mec1723/dev-mec1723.code-workspace create mode 100644 platform/dev-mec1723/memory.x create mode 100644 platform/dev-mec1723/src/board.rs create mode 100644 platform/dev-mec1723/src/clocks.rs create mode 100644 platform/dev-mec1723/src/main.rs create mode 100644 platform/dev-mec1723/supply-chain/audits.toml create mode 100644 platform/dev-mec1723/supply-chain/config.toml create mode 100644 platform/dev-mec1723/supply-chain/imports.lock diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml new file mode 100644 index 0000000..c2d2d53 --- /dev/null +++ b/platform/dev-mec1723/.cargo/config.toml @@ -0,0 +1,21 @@ +[target.thumbv8m.main-none-eabihf] +runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000' + +rustflags = [ + "-C", + "linker=flip-link", + "-C", + "link-arg=-Tlink.x", + "-C", + "link-arg=-Tdefmt.x", + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", + "link-arg=--nmagic", +] + +[build] +target = "thumbv8m.main-none-eabihf" # Cortex-M33 + +[env] +DEFMT_LOG = "trace" diff --git a/platform/dev-mec1723/Cargo.lock b/platform/dev-mec1723/Cargo.lock new file mode 100644 index 0000000..f18e9e6 --- /dev/null +++ b/platform/dev-mec1723/Cargo.lock @@ -0,0 +1,1569 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "aho-corasick" +version = "1.1.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" +dependencies = [ + "memchr", +] + +[[package]] +name = "autocfg" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" + +[[package]] +name = "bare-metal" +version = "0.2.5" +source = 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as when debugging a service) +# [profile.dev.package.dependency-name] +# opt-level = 0 + +[lints.rust] +warnings = "deny" + +[lints.clippy] +correctness = "deny" +perf = "deny" +suspicious = "deny" +style = "deny" + +[dependencies] +cortex-m = { version = "0.7.7", features = [ + "inline-asm", + "critical-section-single-core", +] } +cortex-m-rt = { version = "0.7.3", features = ["device"] } +defmt = "1.0" +defmt-rtt = "1.0" +embassy-executor = { version = "0.10.0", default-features = false, features = [ + "platform-cortex-m", + "executor-thread", + "executor-interrupt", + "defmt", +] } +embassy-microchip = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6", features = [ + "defmt", + "mec1723n_b0_sz", # u_Note: the dev board i have with me says 'SZ' on it + "rt", +] } +uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-services", branch = "v0.2.0", features = [ + "defmt", +] } +static_cell = "2.1.0" +platform-common = { path = "../platform-common", features = ["mock"] } +panic-probe = { version = "1.0.0", features = ["print-defmt"] } + +[package.metadata.cargo-machete] +ignored = ["cortex-m", "cortex-m-rt"] + +# embassy-microchip pulls embassy-time-driver from the embassy-rs git repo, which +# uses `links = "embassy-time"`. Other crates in the dependency graph pull +# embassy-time/embassy-time-driver from crates.io, which would cause a duplicate +# `links` conflict. Force everyone to use the git versions. +[patch.crates-io] +embassy-time = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-time-driver = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-time-queue-utils = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-sync = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-executor = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-futures = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-embedded-hal = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-hal-internal = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } diff --git a/platform/dev-mec1723/build.rs b/platform/dev-mec1723/build.rs new file mode 100644 index 0000000..555cdf6 --- /dev/null +++ b/platform/dev-mec1723/build.rs @@ -0,0 +1,21 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + // Put `memory.x` in our output directory and ensure it's + // on the linker search path. + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + + // By default, Cargo will re-run a build script whenever + // any file in the project changes. By specifying `memory.x` + // here, we ensure the build script is only re-run when + // `memory.x` is changed. + println!("cargo:rerun-if-changed=memory.x"); +} diff --git a/platform/dev-mec1723/dev-mec1723.code-workspace b/platform/dev-mec1723/dev-mec1723.code-workspace new file mode 100644 index 0000000..49244a1 --- /dev/null +++ b/platform/dev-mec1723/dev-mec1723.code-workspace @@ -0,0 +1,23 @@ +{ + "folders": [ + { + "path": "../.." + }, + { + "path": "." + } + ], + "settings": { + "rust-analyzer.checkOnSave": true, + "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", // u_Note: I chose this target because it's what the `mec17xx-pac` repo uses + "rust-analyzer.linkedProjects": [ + "platform/dev-mec1723/Cargo.toml" + ], + "rust-analyzer.check.workspace": false, + "terminal.integrated.cwd": ".", + // + // Variables for launch.json customization + // (grayed out in UI, but can be used in launch.json) + "platform": "dev-mec1723", + }, +} \ No newline at end of file diff --git a/platform/dev-mec1723/memory.x b/platform/dev-mec1723/memory.x new file mode 100644 index 0000000..b4c3aad --- /dev/null +++ b/platform/dev-mec1723/memory.x @@ -0,0 +1,12 @@ +// Datasheet for the chip: https://www.microchip.com/content/dam/mchp/documents/CPG/ProductDocuments/DataSheets/MEC172x-Data-Sheet-DS00003583E.pdf + +MEMORY { + + // u_Notes about FLASH: + // - This assumes the 'Cache SPI Enable' bit is 0, which it is by default. + // - See FIGURE 7-1 on page 180 of the datasheet for more info (384KB comes from 32KB + 352KB. If the 'Cache SPI Enable' bit was 1, FLASH would just be 352KB). + // - Also, the 384K number is supported by https://github.com/embassy-rs/embassy/blob/e9c32931b906649d65fc502fe8e8f2c70ef1e6ab/examples/microchip/memory.x + FLASH : ORIGIN = 0x000C0000, LENGTH = 384K + + RAM : ORIGIN = 0x00118000, LENGTH = 62K +} \ No newline at end of file diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs new file mode 100644 index 0000000..c01cc58 --- /dev/null +++ b/platform/dev-mec1723/src/board.rs @@ -0,0 +1,45 @@ +use embassy_mcxa::{bind_interrupts, clocks::periph_helpers::LpuartClockSel, lpuart}; +use platform_common::board::BoardIo; +use static_cell::ConstStaticCell; + +bind_interrupts!(struct Irqs { + LPUART2 => lpuart::BbqInterruptHandler::; +}); + +const SIZE: usize = 4096; +static RX_BUF: ConstStaticCell<[u8; SIZE]> = ConstStaticCell::new([0u8; SIZE]); +static TX_BUF: ConstStaticCell<[u8; SIZE]> = ConstStaticCell::new([0u8; SIZE]); + +/// Board IO for the dev-mcxa platform. +/// +/// This minimal development board provides a UART interface +/// for ODP service communication. +pub struct Board { + /// UART for ODP service communication. + pub uart: lpuart::LpuartBbq, +} + +impl BoardIo for Board { + type Peripherals = embassy_mcxa::Peripherals; + + fn init(p: Self::Peripherals) -> Self { + let mut config = lpuart::BbqConfig::default(); + config.power = embassy_mcxa::clocks::PoweredClock::NormalEnabledDeepSleepDisabled; + config.source = LpuartClockSel::FroHfDiv; + + let tx_buf = TX_BUF.take(); + let rx_buf = RX_BUF.take(); + + // Create UART instance with DMA channels + let tx_dma = embassy_mcxa::dma::DmaChannel::new(p.DMA0_CH0); + let rx_dma = embassy_mcxa::dma::DmaChannel::new(p.DMA0_CH1); + + let parts = lpuart::BbqParts::new(p.LPUART2, Irqs, p.P2_2, tx_buf, tx_dma, p.P2_3, rx_buf, rx_dma) + .expect("failed to create BbqParts"); + + let lpuart = lpuart::LpuartBbq::new(parts, config, lpuart::BbqRxMode::Efficiency) + .expect("failed to initialize async LPUART"); + + Board { uart: lpuart } + } +} diff --git a/platform/dev-mec1723/src/clocks.rs b/platform/dev-mec1723/src/clocks.rs new file mode 100644 index 0000000..1fc0469 --- /dev/null +++ b/platform/dev-mec1723/src/clocks.rs @@ -0,0 +1,56 @@ +//! Clock configuration for the MCXA dev board. + +use embassy_mcxa::clocks::PoweredClock; +use embassy_mcxa::clocks::config::{ + ClocksConfig, CoreSleep, Div8, FircConfig, FircFreqSel, FlashSleep, MainClockConfig, MainClockSource, + VddDriveStrength, VddLevel, +}; + +/// Build the desired clock tree configuration for the board. +pub fn config() -> ClocksConfig { + let mut cfg = ClocksConfig::default(); + + // Enable 180MHz clock source + let mut fcfg = FircConfig::default(); + fcfg.frequency = FircFreqSel::Mhz180; + fcfg.power = PoweredClock::NormalEnabledDeepSleepDisabled; + fcfg.fro_hf_enabled = true; + fcfg.clk_hf_fundamental_enabled = false; + fcfg.fro_hf_div = Some(const { Div8::from_divisor(4).unwrap() }); + cfg.firc = Some(fcfg); + + // Enable 12M osc + cfg.sirc.fro_12m_enabled = true; + cfg.sirc.fro_lf_div = Some(Div8::no_div()); + cfg.sirc.power = PoweredClock::AlwaysEnabled; + + // Disable 16K osc + cfg.fro16k = None; + + // Disable external osc + cfg.sosc = None; + + // Disable PLL + cfg.spll = None; + + // Feed core from 180M osc + cfg.main_clock = MainClockConfig { + source: MainClockSource::FircHfRoot, + power: PoweredClock::NormalEnabledDeepSleepDisabled, + ahb_clk_div: Div8::no_div(), + }; + + // We don't sleep, set relatively high power + cfg.vdd_power.active_mode.level = VddLevel::OverDriveMode; + cfg.vdd_power.low_power_mode.level = VddLevel::MidDriveMode; + cfg.vdd_power.active_mode.drive = VddDriveStrength::Normal; + cfg.vdd_power.low_power_mode.drive = VddDriveStrength::Low { enable_bandgap: false }; + + // Set "never sleep" mode + cfg.vdd_power.core_sleep = CoreSleep::WfeUngated; + + // Set flash doze, allowing internal flash clocks to be gated on sleep + cfg.vdd_power.flash_sleep = FlashSleep::FlashDoze; + + cfg +} diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs new file mode 100644 index 0000000..0dfac52 --- /dev/null +++ b/platform/dev-mec1723/src/main.rs @@ -0,0 +1,39 @@ +#![no_std] +#![no_main] + +mod board; +mod clocks; + +use board::Board; +use defmt::info; +use defmt_rtt as _; +use embassy_executor::Spawner; +use embassy_mcxa::lpuart; +use panic_probe as _; +use platform_common::board::BoardIo; +use platform_common::mock::MockOdpRelayHandler; +use static_cell::StaticCell; + +#[embassy_executor::task] +async fn uart_service(uart: lpuart::LpuartBbq, relay: MockOdpRelayHandler) { + info!("Starting uart service"); + static UART_SERVICE: StaticCell> = StaticCell::new(); + let uart_service = uart_service::Service::new(relay).unwrap(); + let uart_service = UART_SERVICE.init(uart_service); + + let Err(e) = uart_service::task::uart_service(uart_service, uart).await; + panic!("uart-service error: {:?}", e); +} + +#[embassy_executor::main] +async fn main(spawner: Spawner) { + let mut cfg = embassy_mcxa::config::Config::default(); + cfg.clock_cfg = clocks::config(); + let p = embassy_mcxa::init(cfg); + let board = Board::init(p); + + info!("Hello world from MCXA!"); + + let relay = platform_common::mock::init(spawner).await; + spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); +} diff --git a/platform/dev-mec1723/supply-chain/audits.toml b/platform/dev-mec1723/supply-chain/audits.toml new file mode 100644 index 0000000..4f470da --- /dev/null +++ b/platform/dev-mec1723/supply-chain/audits.toml @@ -0,0 +1,79 @@ + +# cargo-vet audits file + +[[audits.embassy-embedded-hal]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.6.0 -> 0.6.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: Cargo.toml dep version bump only (embassy-hal-internal 0.4.0->0.5.0). No code changes, no unsafe. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-executor]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.10.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.10.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: added armv8r target, dep version bumps, doc comment fixes. No new unsafe, no new imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-executor-macros]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.8.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.8.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: proc macro hygiene fix — renamed POOL_SIZE to __POOL_SIZE to avoid name collisions. No new unsafe, generated code unchanged. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-executor-timer-queue]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.1.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.1.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: changelog fix and edition 2021->2024. No code changes, no unsafe. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-futures]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.1.2 -> 0.1.2@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: edition 2021->2024, explicit feature declarations. No code changes, no unsafe. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-hal-internal]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.5.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.5.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: new aligned.rs module (4 transmute calls, all behind alignment assertions — sound), ring buffer Reader/Writer iterators (3 unsafe blocks for slice::from_raw_parts_mut and ptr reborrow — consistent with existing invariants). No new powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-mcxa]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +version = "0.1.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Co-owned by ODP, trusted publisher (Dirbaio from Embedded WG). Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-sync]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.8.0 -> 0.8.0@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: new rpc_service module (type-erased FnOnce dispatch, well-documented unsafe with clear invariants), OnceLock memory ordering fix (Relaxed->Acquire/Release), priority_channel bug fix, pubsub Send/Sync wrappers with proper bounds, pipe try_write_all. No new powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-time]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.5.1@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.5.1@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: added 62.5MHz tick rate, replaced custom div_ceil with u64::div_ceil, added core::error::Error impl for TimeoutError. No new unsafe, removed redundant helper fn. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-time-driver]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.2.2 -> 0.2.2@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "Delta: added 62.5MHz tick rate feature flag. No unsafe, no new imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.embassy-time-queue-utils]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +delta = "0.3.2@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.3.2@git:bef4118731ac69092bee4489240f59c89af0d944" +importable = false +notes = "No diff between crates.io and git versions — identical source. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" diff --git a/platform/dev-mec1723/supply-chain/config.toml b/platform/dev-mec1723/supply-chain/config.toml new file mode 100644 index 0000000..b0da212 --- /dev/null +++ b/platform/dev-mec1723/supply-chain/config.toml @@ -0,0 +1,358 @@ + +# cargo-vet config file + +[cargo-vet] +version = "0.10" + +[imports.bytecode-alliance] +url = "https://raw.githubusercontent.com/bytecodealliance/wasmtime/main/supply-chain/audits.toml" + +[imports.google] +url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" + +[imports.mozilla] +url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" + +[imports.open-device-partnership] +url = "https://raw.githubusercontent.com/OpenDevicePartnership/embedded-services/main/supply-chain/audits.toml" + +[policy.embassy-embedded-hal] +audit-as-crates-io = true + +[policy.embassy-executor] +audit-as-crates-io = true + +[policy.embassy-executor-macros] +audit-as-crates-io = true + +[policy.embassy-executor-timer-queue] +audit-as-crates-io = true + +[policy.embassy-futures] +audit-as-crates-io = true + +[policy.embassy-hal-internal] +audit-as-crates-io = true + +[policy.embassy-mcxa] +audit-as-crates-io = true + +[policy.embassy-sync] +audit-as-crates-io = true + +[policy.embassy-time] +audit-as-crates-io = true + +[policy.embassy-time-driver] +audit-as-crates-io = true + +[policy.embassy-time-queue-utils] +audit-as-crates-io = true + +[[exemptions.aho-corasick]] +version = "1.1.4" +criteria = "safe-to-deploy" + +[[exemptions.bare-metal]] +version = "0.2.5" +criteria = "safe-to-deploy" + +[[exemptions.bbqueue]] +version = "0.7.0" +criteria = "safe-to-deploy" + +[[exemptions.bitfield]] +version = "0.13.2" +criteria = "safe-to-deploy" + +[[exemptions.bq40z50-rx]] +version = "0.8.1" +criteria = "safe-to-deploy" + +[[exemptions.cc]] +version = "1.2.61" +criteria = "safe-to-deploy" + +[[exemptions.cfg-if]] +version = "1.0.4" +criteria = "safe-to-deploy" + +[[exemptions.cfg_aliases]] +version = "0.2.1" +criteria = "safe-to-deploy" + +[[exemptions.convert_case]] +version = "0.11.0" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m]] +version = "0.7.7" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m-rt]] +version = "0.7.5" +criteria = "safe-to-deploy" + +[[exemptions.cortex-m-rt-macros]] +version = "0.7.5" +criteria = "safe-to-deploy" + +[[exemptions.critical-section]] +version = "1.2.0" +criteria = "safe-to-deploy" + +[[exemptions.darling]] +version = "0.20.11" +criteria = "safe-to-deploy" + +[[exemptions.darling_core]] +version = "0.20.11" +criteria = "safe-to-deploy" + +[[exemptions.darling_macro]] +version = "0.20.11" +criteria = "safe-to-deploy" + +[[exemptions.defmt]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.defmt-macros]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.defmt-parser]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.defmt-rtt]] +version = "1.1.0" +criteria = "safe-to-deploy" + +[[exemptions.document-features]] +version = "0.2.12" +criteria = "safe-to-deploy" + +[[exemptions.embassy-executor]] +version = "0.10.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" +criteria = "safe-to-deploy" + +[[exemptions.embassy-executor-macros]] +version = "0.8.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" +criteria = "safe-to-deploy" + +[[exemptions.embassy-executor-timer-queue]] +version = "0.1.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" +criteria = "safe-to-deploy" + +[[exemptions.embassy-hal-internal]] +version = "0.5.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" +criteria = "safe-to-deploy" + +[[exemptions.embassy-time]] +version = "0.5.1@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" +criteria = "safe-to-deploy" + +[[exemptions.embassy-time-queue-utils]] +version = "0.3.2@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" +criteria = "safe-to-deploy" + +[[exemptions.embedded-hal]] +version = "0.2.7" +criteria = "safe-to-deploy" + +[[exemptions.embedded-sensors-hal]] +version = "0.1.1" +criteria = "safe-to-deploy" + +[[exemptions.find-msvc-tools]] +version = "0.1.9" +criteria = "safe-to-deploy" + +[[exemptions.futures-core]] +version = "0.3.32" +criteria = "safe-to-deploy" + +[[exemptions.futures-sink]] +version = "0.3.32" +criteria = "safe-to-deploy" + +[[exemptions.generator]] +version = "0.8.8" +criteria = "safe-to-deploy" + +[[exemptions.grounded]] +version = "0.2.1" +criteria = "safe-to-deploy" + +[[exemptions.hashbrown]] +version = "0.17.0" +criteria = "safe-to-deploy" + +[[exemptions.heapless]] +version = "0.9.3" +criteria = "safe-to-deploy" + +[[exemptions.ident_case]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.indexmap]] +version = "2.14.0" +criteria = "safe-to-deploy" + +[[exemptions.libc]] +version = "0.2.186" +criteria = "safe-to-deploy" + +[[exemptions.litrs]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.loom]] +version = "0.7.2" +criteria = "safe-to-deploy" + +[[exemptions.maitake-sync]] +version = "0.3.0" +criteria = "safe-to-deploy" + +[[exemptions.memchr]] +version = "2.8.0" +criteria = "safe-to-deploy" + +[[exemptions.once_cell]] +version = "1.21.4" +criteria = "safe-to-deploy" + +[[exemptions.panic-probe]] +version = "1.0.0" +criteria = "safe-to-deploy" + +[[exemptions.paste]] +version = "1.0.15" +criteria = "safe-to-deploy" + +[[exemptions.pin-project]] +version = "1.1.12" +criteria = "safe-to-deploy" + +[[exemptions.pin-project-internal]] +version = "1.1.12" +criteria = "safe-to-deploy" + +[[exemptions.pin-project-lite]] +version = "0.2.17" +criteria = "safe-to-deploy" + +[[exemptions.portable-atomic]] +version = "1.13.1" +criteria = "safe-to-deploy" + +[[exemptions.rand_core]] +version = "0.10.1" +criteria = "safe-to-deploy" + +[[exemptions.regex]] +version = "1.12.3" +criteria = "safe-to-deploy" + +[[exemptions.regex-automata]] +version = "0.4.14" +criteria = "safe-to-deploy" + +[[exemptions.regex-syntax]] +version = "0.8.10" +criteria = "safe-to-deploy" + +[[exemptions.rustc_version]] +version = "0.2.3" +criteria = "safe-to-deploy" + +[[exemptions.rustversion]] +version = "1.0.22" +criteria = "safe-to-deploy" + +[[exemptions.scoped-tls]] +version = "1.0.1" +criteria = "safe-to-deploy" + +[[exemptions.semver]] +version = "0.9.0" +criteria = "safe-to-deploy" + +[[exemptions.semver-parser]] +version = "0.7.0" +criteria = "safe-to-deploy" + +[[exemptions.stable_deref_trait]] +version = "1.2.1" +criteria = "safe-to-deploy" + +[[exemptions.subenum]] +version = "1.2.0" +criteria = "safe-to-deploy" + +[[exemptions.syn]] +version = "2.0.117" +criteria = "safe-to-deploy" + +[[exemptions.thiserror]] +version = "2.0.18" +criteria = "safe-to-deploy" + +[[exemptions.thiserror-impl]] +version = "2.0.18" +criteria = "safe-to-deploy" + +[[exemptions.tracing]] +version = "0.1.44" +criteria = "safe-to-deploy" + +[[exemptions.tracing-attributes]] +version = "0.1.31" +criteria = "safe-to-deploy" + +[[exemptions.tracing-core]] +version = "0.1.36" +criteria = "safe-to-deploy" + +[[exemptions.tracing-subscriber]] +version = "0.3.23" +criteria = "safe-to-deploy" + +[[exemptions.unicode-ident]] +version = "1.0.24" +criteria = "safe-to-deploy" + +[[exemptions.unicode-segmentation]] +version = "1.13.2" +criteria = "safe-to-deploy" + +[[exemptions.vcell]] +version = "0.1.3" +criteria = "safe-to-deploy" + +[[exemptions.volatile-register]] +version = "0.2.2" +criteria = "safe-to-deploy" + +[[exemptions.windows-link]] +version = "0.2.1" +criteria = "safe-to-deploy" + +[[exemptions.windows-result]] +version = "0.4.1" +criteria = "safe-to-deploy" + +[[exemptions.windows-sys]] +version = "0.61.2" +criteria = "safe-to-deploy" + +[[exemptions.zerocopy]] +version = "0.8.48" +criteria = "safe-to-deploy" + +[[exemptions.zerocopy-derive]] +version = "0.8.48" +criteria = "safe-to-deploy" diff --git a/platform/dev-mec1723/supply-chain/imports.lock b/platform/dev-mec1723/supply-chain/imports.lock new file mode 100644 index 0000000..5cbae2f --- /dev/null +++ b/platform/dev-mec1723/supply-chain/imports.lock @@ -0,0 +1,869 @@ + +# cargo-vet imports lock + +[[audits.bytecode-alliance.audits.bitflags]] +who = "Jamey Sharp " +criteria = "safe-to-deploy" +delta = "2.1.0 -> 2.2.1" +notes = """ +This version adds unsafe impls of traits from the bytemuck crate when built +with that library enabled, but I believe the impls satisfy the documented +safety requirements for bytemuck. The other changes are minor. +""" + +[[audits.bytecode-alliance.audits.bitflags]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "2.3.2 -> 2.3.3" +notes = """ +Nothing outside the realm of what one would expect from a bitflags generator, +all as expected. +""" + +[[audits.bytecode-alliance.audits.bitflags]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "2.4.1 -> 2.6.0" +notes = """ +Changes in how macros are invoked and various bits and pieces of macro-fu. +Otherwise no major changes and nothing dealing with `unsafe`. +""" + +[[audits.bytecode-alliance.audits.bitflags]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "2.7.0 -> 2.9.4" +notes = "Tweaks to the macro, nothing out of order." + +[[audits.bytecode-alliance.audits.bitflags]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "2.10.0 -> 2.11.1" +notes = "Minor updates, nothing awry here." + +[[audits.bytecode-alliance.audits.embedded-io]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "0.4.0" +notes = "No `unsafe` code and only uses `std` in ways one would expect the crate to do so." + +[[audits.bytecode-alliance.audits.embedded-io]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.0 -> 0.6.1" +notes = "Major updates, but almost all safe code. Lots of pruning/deletions, nothing out of the ordrinary." + +[[audits.bytecode-alliance.audits.heck]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.4.1 -> 0.5.0" +notes = "Minor changes for a `no_std` upgrade but otherwise everything looks as expected." + +[[audits.bytecode-alliance.audits.matchers]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.1.0" + +[[audits.bytecode-alliance.audits.matchers]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.0 -> 0.2.0" +notes = "Some unsafe code, but not more than before. Nothing awry." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.46.0" +notes = "one use of unsafe to call windows specific api to get console handle." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.46.0 -> 0.50.1" +notes = "Lots of stylistic/rust-related changes, plus new features, but nothing out of the ordrinary." + +[[audits.bytecode-alliance.audits.nu-ansi-term]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.50.1 -> 0.50.3" +notes = "CI changes, Rust changes, nothing out of the ordinary." + +[[audits.bytecode-alliance.audits.num-traits]] +who = "Andrew Brown " +criteria = "safe-to-deploy" +version = "0.2.19" +notes = "As advertised: a numeric library. The only `unsafe` is from some float-to-int conversions, which seems expected." + +[[audits.bytecode-alliance.audits.sharded-slab]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "0.1.4" +notes = "I always really enjoy reading eliza's code, she left perfect comments at every use of unsafe." + +[[audits.bytecode-alliance.audits.shlex]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "1.1.0" +notes = "Only minor `unsafe` code blocks which look valid and otherwise does what it says on the tin." + +[[audits.bytecode-alliance.audits.smallvec]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "1.13.2 -> 1.14.0" +notes = "Minor new feature, nothing out of the ordinary." + +[[audits.bytecode-alliance.audits.static_assertions]] +who = "Andrew Brown " +criteria = "safe-to-deploy" +version = "1.1.0" +notes = "No dependencies and completely a compile-time crate as advertised. Uses `unsafe` in one module as a compile-time check only: `mem::transmute` and `ptr::write` are wrapped in an impossible-to-run closure." + +[[audits.bytecode-alliance.audits.thread_local]] +who = "Pat Hickey " +criteria = "safe-to-deploy" +version = "1.1.4" +notes = "uses unsafe to implement thread local storage of objects" + +[[audits.bytecode-alliance.audits.tracing-log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +version = "0.1.3" +notes = """ +This is a standard adapter between the `log` ecosystem and the `tracing` +ecosystem. There's one `unsafe` block in this crate and it's well-scoped. +""" + +[[audits.bytecode-alliance.audits.tracing-log]] +who = "Alex Crichton " +criteria = "safe-to-deploy" +delta = "0.1.3 -> 0.2.0" +notes = "Nothing out of the ordinary, a typical major version update and nothing awry." + +[[audits.google.audits.autocfg]] +who = "Manish Goregaokar " +criteria = "safe-to-deploy" +version = "1.4.0" +notes = "Contains no unsafe" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.bitflags]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.3.2" +notes = """ +Security review of earlier versions of the crate can be found at +(Google-internal, sorry): go/image-crate-chromium-security-review + +The crate exposes a function marked as `unsafe`, but doesn't use any +`unsafe` blocks (except for tests of the single `unsafe` function). I +think this justifies marking this crate as `ub-risk-1`. + +Additional review comments can be found at https://crrev.com/c/4723145/31 +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.byteorder]] +who = "danakj " +criteria = "safe-to-deploy" +version = "1.5.0" +notes = "Unsafe review in https://crrev.com/c/5838022" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.equivalent]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +version = "1.0.1" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.equivalent]] +who = "Jonathan Hao " +criteria = "safe-to-deploy" +delta = "1.0.1 -> 1.0.2" +notes = "No changes to any .rs files or Rust code." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.heck]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "0.4.1" +notes = """ +Grepped for `-i cipher`, `-i crypto`, `'\bfs\b'``, `'\bnet\b'``, `'\bunsafe\b'`` +and there were no hits. + +`heck` (version `0.3.3`) has been added to Chromium in +https://source.chromium.org/chromium/chromium/src/+/28841c33c77833cc30b286f9ae24c97e7a8f4057 +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.lazy_static]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.4.0" +notes = ''' +I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits. + +There are two places where `unsafe` is used. Unsafe review notes can be found +in https://crrev.com/c/5347418. + +This crate has been added to Chromium in https://crrev.com/c/3321895. +''' +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.lazy_static]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.4.0 -> 1.5.0" +notes = "Unsafe review notes: https://crrev.com/c/5650836" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.log]] +who = "danakj " +criteria = "safe-to-deploy" +version = "0.4.22" +notes = """ +Unsafe review in https://docs.google.com/document/d/1IXQbD1GhTRqNHIGxq6yy7qHqxeO4CwN5noMFXnqyDIM/edit?usp=sharing + +Unsafety is generally very well-documented, with one exception, which we +describe in the review doc. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.log]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "0.4.22 -> 0.4.25" +notes = "No impact on `unsafe` usage in `lib.rs`." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.log]] +who = "Daniel Cheng " +criteria = "safe-to-deploy" +delta = "0.4.25 -> 0.4.26" +notes = "Only trivial code and documentation changes." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +version = "1.0.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 0.1.3" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.nb]] +who = "George Burgess IV " +criteria = "safe-to-deploy" +delta = "1.0.0 -> 1.1.0" +aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +version = "1.0.78" +notes = """ +Grepped for "crypt", "cipher", "fs", "net" - there were no hits +(except for a benign "fs" hit in a doc comment) + +Notes from the `unsafe` review can be found in https://crrev.com/c/5385745. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.0.78 -> 1.0.79" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Adrian Taylor " +criteria = "safe-to-deploy" +delta = "1.0.79 -> 1.0.80" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Dustin J. Mitchell " +criteria = "safe-to-deploy" +delta = "1.0.80 -> 1.0.81" +notes = "Comment changes only" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "danakj " +criteria = "safe-to-deploy" +delta = "1.0.81 -> 1.0.82" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Dustin J. Mitchell " +criteria = "safe-to-deploy" +delta = "1.0.82 -> 1.0.83" +notes = "Substantive change is replacing String with Box, saving memory." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.0.83 -> 1.0.84" +notes = "Only doc comment changes in `src/lib.rs`." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "danakj@chromium.org" +criteria = "safe-to-deploy" +delta = "1.0.84 -> 1.0.85" +notes = "Test-only changes." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Lukasz Anforowicz " +criteria = "safe-to-deploy" +delta = "1.0.85 -> 1.0.86" +notes = """ +Comment-only changes in `build.rs`. +Reordering of `Cargo.toml` entries. +Just bumping up the version number in `lib.rs`. +Config-related changes in `test_size.rs`. +""" +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "danakj " +criteria = "safe-to-deploy" +delta = "1.0.86 -> 1.0.87" +notes = "No new unsafe interactions." +aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" + +[[audits.google.audits.proc-macro2]] +who = "Liza Burakova ", + "Erich Gubler ", +] +criteria = "safe-to-deploy" +delta = "2.6.0 -> 2.7.0" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.bitflags]] +who = "Benjamin VanderSloot " +criteria = "safe-to-deploy" +delta = "2.9.4 -> 2.10.0" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.fnv]] +who = "Bobby Holley " +criteria = "safe-to-deploy" +version = "1.0.7" +notes = "Simple hasher implementation with no unsafe code." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.log]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "0.4.26 -> 0.4.29" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.proc-macro-error-attr2]] +who = "Kagami Sascha Rosylight " +criteria = "safe-to-deploy" +version = "2.0.0" +notes = "No unsafe block." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.proc-macro-error2]] +who = "Kagami Sascha Rosylight " +criteria = "safe-to-deploy" +version = "2.0.1" +notes = "No unsafe block with a lovely `#![forbid(unsafe_code)]`." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.proc-macro2]] +who = "Jan-Erik Rediger " +criteria = "safe-to-deploy" +delta = "1.0.94 -> 1.0.106" +aggregated-from = "https://raw.githubusercontent.com/mozilla/glean/main/supply-chain/audits.toml" + +[[audits.mozilla.audits.quote]] +who = "Jan-Erik Rediger " +criteria = "safe-to-deploy" +delta = "1.0.40 -> 1.0.45" +aggregated-from = "https://raw.githubusercontent.com/mozilla/glean/main/supply-chain/audits.toml" + +[[audits.mozilla.audits.serde_core]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.0.226 -> 1.0.227" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.serde_core]] +who = "Jan-Erik Rediger " +criteria = "safe-to-deploy" +delta = "1.0.227 -> 1.0.228" +aggregated-from = "https://raw.githubusercontent.com/mozilla/glean/main/supply-chain/audits.toml" + +[[audits.mozilla.audits.sharded-slab]] +who = "Mark Hammond " +criteria = "safe-to-deploy" +delta = "0.1.4 -> 0.1.7" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.shlex]] +who = "Max Inden " +criteria = "safe-to-deploy" +delta = "1.1.0 -> 1.3.0" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.smallvec]] +who = "Erich Gubler " +criteria = "safe-to-deploy" +delta = "1.14.0 -> 1.15.1" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.strsim]] +who = "Ben Dean-Kawamura " +criteria = "safe-to-deploy" +delta = "0.10.0 -> 0.11.1" +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.mozilla.audits.void]] +who = "Bobby Holley " +criteria = "safe-to-deploy" +version = "1.0.2" +notes = "Very small crate, just hosts the Void type for easier cross-crate interfacing." +aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" + +[[audits.open-device-partnership.audits.autocfg]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "1.4.0 -> 1.5.0" +notes = "No unsafe, no build.rs, no network access; delta adds edition-aware rustc probing and best-effort probe-file cleanup only. Assisted-by: copilot-cli:GPT-5.3-Codex cargo-vet" + +[[audits.open-device-partnership.audits.bitfield]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.13.2 -> 0.15.0" +notes = "Delta audit: BitRange/Bit traits split into read-only and mutable variants (BitRangeMut/BitMut); added mask constant generation; clippy fixes; MSRV bump. No unsafe, no build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.bitfield]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.15.0 -> 0.17.0" +notes = "Delta: adds bitwise op derives, constructor derives, arbitrary visibility. Pure declarative macros. No unsafe, no build script. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.bitfield-struct]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.10.1" +notes = "Proc-macro crate generating safe bitfield structs. No unsafe, no build script. Standard proc-macro deps only. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.bitfield-struct]] +who = "matteotullo " +criteria = "safe-to-deploy" +delta = "0.10.1 -> 0.12.1" +notes = "Adds hash and bitenum derives, mostly parsing and refactoring changes. No code execution nor writing to the filesystem." + +[[audits.open-device-partnership.audits.const-init]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "1.0.0" + +[[audits.open-device-partnership.audits.cordyceps]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.3.4" +notes = "Intrusive data structures crate (no_std). ~115 unsafe blocks, all necessary for intrusive linked list/queue/stack ops. Correct patterns: addr_of_mut, proper atomic orderings, Vyukov MPSC algorithm. No build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.defmt]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.3.100" +notes = "Compatibility shim: no_std crate that re-exports defmt 1.x items for 0.3 API compatibility. No unsafe code, no build script, no powerful imports, no logic - pure pub-use re-exports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.device-driver]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "1.0.7" +notes = "no_std device driver toolkit. Unsafe limited to ops.rs bitfield load/store using get_unchecked with documented invariants; fuzz-tested against bitvec. No build script, no proc macros, no filesystem/network/process access. Assisted-by: copilot-chat:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.device-driver]] +who = "Adam Sasine " +criteria = "safe-to-deploy" +delta = "1.0.7 -> 1.0.9" +notes = "Fixes compilation bugs for large registers but does not change invariants or testing strategy." + +[[audits.open-device-partnership.audits.embassy-embedded-hal]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.5.0" +notes = "No unsafe, no build script, no proc macros. no_std shared bus/flash partition utilities for embedded-hal traits. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embassy-embedded-hal]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.5.0 -> 0.6.0" +notes = "No unsafe code, no build script, no powerful imports. Added Clone for I2C devices. Updated embassy dependencies (embassy-sync 0.7→0.8, embassy-hal-internal 0.3→0.4, embassy-time 0.5→0.5.1). All changes safe." + +[[audits.open-device-partnership.audits.embassy-futures]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.1.2" +notes = "no_std future combinators. All unsafe is pin-projection and no-op RawWaker - reviewed and sound. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embassy-sync]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.8.0" +notes = "no_std async sync primitives. Substantial unsafe for UnsafeCell-based interiors and Send/Sync impls -- all reviewed and sound, guarded by RawMutex/critical_section. Build script only reads TARGET env var. No proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embassy-time-driver]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.2.1" +notes = "no_std driver trait for embassy-time. Minimal unsafe for extern Rust FFI calls (sound via links key). Empty build.rs. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embassy-time-driver]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.2.1 -> 0.2.2" +notes = "Rust 2024 edition update with 375kHz tick rate feature. Empty build.rs, no unsafe code, no powerful imports." + +[[audits.open-device-partnership.audits.embedded-batteries]] +who = "matteotullo " +criteria = "safe-to-deploy" +version = "0.3.4" +notes = "ODP crates are always trusted." + +[[audits.open-device-partnership.audits.embedded-batteries-async]] +who = "matteotullo " +criteria = "safe-to-deploy" +version = "0.3.4" +notes = "ODP crates are always trusted." + +[[audits.open-device-partnership.audits.embedded-crc-macros]] +who = "Matteo Tullo " +criteria = "safe-to-deploy" +version = "1.0.0" + +[[audits.open-device-partnership.audits.embedded-fans]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +version = "0.1.0" +notes = "ODP crates are always trusted." + +[[audits.open-device-partnership.audits.embedded-fans-async]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +version = "0.2.0" +notes = "ODP crates are always trusted." + +[[audits.open-device-partnership.audits.embedded-hal]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.2.7 -> 1.0.0" +notes = "Pure no_std trait crate. Complete API redesign for 1.0: removed nb-based traits, CAN module, all unsafe code. Only defines traits/enums/types for digital, I2C, SPI, PWM, delay. No build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-hal-async]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "1.0.0" +notes = "no_std async HAL trait definitions. No unsafe in library. Build script only runs rustc --version. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-hal-nb]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "1.0.0" +notes = "no_std trait-only crate. No unsafe, no build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-io]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.6.1 -> 0.7.1" +notes = "No unsafe, no build script, no I/O. Trait evolution: Error requires core::error::Error (MSRV 1.81), BufRead: Read, Seek gains seek_relative, new VecDeque impls, defmt bumped to v1. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-io-async]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.6.1" +notes = "No unsafe. Build script only detects nightly via rustc --version. Pure async trait definitions for embedded I/O. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-io-async]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.6.1 -> 0.7.0" +notes = "Delta 0.6.1->0.7.0: No unsafe. Build script removed (AFIT now stable). flush() made required, BufRead requires Read, new VecDeque impls. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-mcu-hal]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.2.0" +notes = "Trait-based MCU HAL with zero unsafe code. No build script or powerful imports. Pure trait design with optional chrono/defmt features. Ideal for embedded controllers." + +[[audits.open-device-partnership.audits.embedded-sensors-hal-async]] +who = "Kurtis Dinelle " +criteria = "safe-to-deploy" +version = "0.3.0" +notes = "ODP crates are always trusted." + +[[audits.open-device-partnership.audits.embedded-storage]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.3.1" +notes = "Pure no_std storage abstraction traits. deny(unsafe_code), no build script, no dependencies, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.embedded-storage-async]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.4.1" +notes = "Pure no_std async trait definitions for NOR flash storage. No unsafe code, no build script, no powerful imports. Only dependency is embedded-storage. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.hash32]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.3.1" +notes = "no_std 32-bit hashing (FNV, MurmurHash3). ~10 unsafe blocks in murmur3.rs for MaybeUninit buffer handling - all sound. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.heapless]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.8.0" +notes = "no_std fixed-capacity data structures. Extensive unsafe for MaybeUninit buffer management, lock-free queues (Vyukov MPMC, SPSC), and Treiber stack memory pools with ABA prevention. Patterns mirror std or published algorithms. Build script probes for atomic/LLSC support. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.mutex-traits]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "1.0.1" + +[[audits.open-device-partnership.audits.mycelium-bitfield]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.1.5" +notes = "Pure safe no_std bitfield macro crate. No unsafe code, no build script, no proc macros, no dependencies, no powerful imports. Only core:: types used. Assisted-by: copilot-chat:claude-opus-4.6 cargo-vet" + +[[audits.open-device-partnership.audits.num_enum]] +who = "Matteo Tullo " +criteria = "safe-to-deploy" +version = "0.7.4" + +[[audits.open-device-partnership.audits.num_enum]] +who = "Billy Price " +criteria = "safe-to-deploy" +delta = "0.7.4 -> 0.7.5" +notes = "Looks like this is just uptaking a new version of num_enum_derive" + +[[audits.open-device-partnership.audits.num_enum]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.7.5 -> 0.7.6" +notes = "Version bump with test infrastructure updates. No unsafe code, no build script, no powerful imports. Purely additive test changes." + +[[audits.open-device-partnership.audits.num_enum_derive]] +who = "Matteo Tullo " +criteria = "safe-to-deploy" +version = "0.7.4" + +[[audits.open-device-partnership.audits.num_enum_derive]] +who = "Billy Price " +criteria = "safe-to-deploy" +delta = "0.7.4 -> 0.7.5" +notes = "Looks like mostly improvements to error messaging" + +[[audits.open-device-partnership.audits.num_enum_derive]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "0.7.5 -> 0.7.6" +notes = "Minor update adding byte literal support for enum discriminants. No unsafe code, no build script, no powerful imports." + +[[audits.open-device-partnership.audits.rand_core]] +who = "Billy Price " +criteria = "safe-to-deploy" +delta = "0.6.4 -> 0.9.5" + +[[audits.open-device-partnership.audits.serde]] +who = "Robert Zieba " +criteria = "safe-to-deploy" +version = "1.0.228" +notes = "Changes are mostly a reorganization of the internal module structure" + +[[audits.open-device-partnership.audits.serde_core]] +who = "Robert Zieba " +criteria = "safe-to-deploy" +version = "1.0.226" + +[[audits.open-device-partnership.audits.serde_derive]] +who = "Robert Zieba " +criteria = "safe-to-deploy" +version = "1.0.228" +notes = "Diff is clean-up in proc macros" + +[[audits.open-device-partnership.audits.smbus-pec]] +who = "Matteo Tullo " +criteria = "safe-to-deploy" +version = "1.0.1" + +[[audits.open-device-partnership.audits.static_cell]] +who = "Robert Zieba " +criteria = "safe-to-deploy" +version = "2.1.1" + +[[audits.open-device-partnership.audits.thread_local]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +delta = "1.1.4 -> 1.1.9" +notes = "No build script, no FS/net/process capability expansion; unsafe refactor to lock-free insertion and nightly TLS path appears sound on review. Assisted-by: copilot-cli:GPT-5.3-Codex cargo-vet" + +[[audits.open-device-partnership.audits.uuid]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "1.17.0" + +[[audits.open-device-partnership.audits.valuable]] +who = "Jerry Xie " +criteria = "safe-to-deploy" +version = "0.1.1" +notes = "No unsafe code; build.rs only sets target atomic cfg via env; no fs/net/process capability use observed; behavior matches value-inspection purpose. Assisted-by: copilot-cli:GPT-5.3-Codex cargo-vet" From 0d3ee2bf27ce4448a58aea580f1c9b09a13ff106 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 16:00:10 -0700 Subject: [PATCH 02/15] board.rs updated --- platform/dev-mec1723/Cargo.lock | 258 ++---- platform/dev-mec1723/src/board.rs | 46 +- platform/dev-mec1723/src/main.rs | 4 +- platform/dev-mec1723/supply-chain/audits.toml | 79 -- platform/dev-mec1723/supply-chain/config.toml | 358 -------- .../dev-mec1723/supply-chain/imports.lock | 869 ------------------ 6 files changed, 88 insertions(+), 1526 deletions(-) delete mode 100644 platform/dev-mec1723/supply-chain/audits.toml delete mode 100644 platform/dev-mec1723/supply-chain/config.toml delete mode 100644 platform/dev-mec1723/supply-chain/imports.lock diff --git a/platform/dev-mec1723/Cargo.lock b/platform/dev-mec1723/Cargo.lock index f18e9e6..72e55d9 100644 --- a/platform/dev-mec1723/Cargo.lock +++ b/platform/dev-mec1723/Cargo.lock @@ -17,6 +17,12 @@ version = "1.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" +[[package]] +name = "az" +version = "1.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "be5eb007b7cacc6c660343e96f650fedf4b5a77512399eb952ca6642cf8d13f7" + [[package]] name = "bare-metal" version = "0.2.5" @@ -62,17 +68,6 @@ dependencies = [ "num_enum", ] -[[package]] -name = "bbqueue" -version = "0.7.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "68917624e17aad88607cb5a5936f6da9b607c48c711e4e9ed101e7189aed28c2" -dependencies = [ - "const-init", - "critical-section", - "maitake-sync", -] - [[package]] name = "bit-register" version = "0.1.0" @@ -129,6 +124,12 @@ dependencies = [ "smbus-pec", ] +[[package]] +name = "bytemuck" +version = "1.25.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "c8efb64bd706a16a1bdde310ae86b351e4d21550d98d056f22f8a7f7a2183fec" + [[package]] name = "byteorder" version = "1.5.0" @@ -151,27 +152,6 @@ version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" -[[package]] -name = "cfg_aliases" -version = "0.2.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "613afe47fcd5fac7ccf1db93babcb082c5994d996f20b8b159f2ad1658eb5724" - -[[package]] -name = "const-init" -version = "1.0.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4bd422bfb4f24a97243f60b6a4443e63d810c925d8da4bb2d8fde26a7c1d57ec" - -[[package]] -name = "convert_case" -version = "0.11.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "affbf0190ed2caf063e3def54ff444b449371d55c58e513a95ab98eca50adb49" -dependencies = [ - "unicode-segmentation", -] - [[package]] name = "cordyceps" version = "0.3.4" @@ -221,6 +201,12 @@ version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b" +[[package]] +name = "crunchy" +version = "0.2.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "460fbee9c2c2f33933d720630a6a0bac33ba7053db5344fac858d4b8952d77d5" + [[package]] name = "darling" version = "0.20.11" @@ -308,7 +294,7 @@ dependencies = [ ] [[package]] -name = "dev-mcxa" +name = "dev-mec1723" version = "0.1.0" dependencies = [ "cortex-m", @@ -316,7 +302,7 @@ dependencies = [ "defmt 1.0.1", "defmt-rtt", "embassy-executor", - "embassy-mcxa", + "embassy-microchip", "panic-probe", "platform-common", "static_cell", @@ -345,7 +331,7 @@ dependencies = [ [[package]] name = "embassy-embedded-hal" version = "0.6.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "embassy-futures", "embassy-hal-internal", @@ -361,7 +347,7 @@ dependencies = [ [[package]] name = "embassy-executor" version = "0.10.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "cordyceps", "cortex-m", @@ -375,7 +361,7 @@ dependencies = [ [[package]] name = "embassy-executor-macros" version = "0.8.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "darling", "proc-macro2", @@ -386,36 +372,35 @@ dependencies = [ [[package]] name = "embassy-executor-timer-queue" version = "0.1.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" [[package]] name = "embassy-futures" version = "0.1.2" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" [[package]] name = "embassy-hal-internal" version = "0.5.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "cortex-m", "critical-section", + "defmt 1.0.1", "num-traits", ] [[package]] -name = "embassy-mcxa" +name = "embassy-microchip" version = "0.1.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ - "bbqueue", - "convert_case", "cortex-m", "cortex-m-rt", "critical-section", "defmt 1.0.1", + "document-features", "embassy-embedded-hal", - "embassy-executor", "embassy-futures", "embassy-hal-internal", "embassy-sync", @@ -428,27 +413,15 @@ dependencies = [ "embedded-hal-nb", "embedded-io 0.7.1", "embedded-io-async 0.7.0", - "embedded-storage", - "grounded", - "heapless 0.9.3", - "indexmap", - "maitake-sync", + "fixed", + "mec17xx-pac", "nb 1.1.0", - "nxp-pac", - "paste", - "proc-macro2", - "quote", - "rand_core 0.10.1", - "rand_core 0.6.4", - "rand_core 0.9.5", - "regex", - "syn", ] [[package]] name = "embassy-sync" version = "0.8.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "cfg-if", "critical-section", @@ -462,7 +435,7 @@ dependencies = [ [[package]] name = "embassy-time" version = "0.5.1" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "cfg-if", "critical-section", @@ -478,7 +451,7 @@ dependencies = [ [[package]] name = "embassy-time-driver" version = "0.2.2" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "document-features", ] @@ -486,7 +459,7 @@ dependencies = [ [[package]] name = "embassy-time-queue-utils" version = "0.3.2" -source = "git+https://github.com/embassy-rs/embassy?rev=bef4118731ac69092bee4489240f59c89af0d944#bef4118731ac69092bee4489240f59c89af0d944" +source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" dependencies = [ "embassy-executor-timer-queue", "heapless 0.9.3", @@ -670,12 +643,6 @@ dependencies = [ "embedded-storage", ] -[[package]] -name = "equivalent" -version = "1.0.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" - [[package]] name = "espi-device" version = "0.1.0" @@ -695,6 +662,18 @@ version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" +[[package]] +name = "fixed" +version = "1.31.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9af2cbf772fa6d1c11358f92ef554cb6b386201210bcf0e91fb7fba8a907fb40" +dependencies = [ + "az", + "bytemuck", + "half", + "typenum", +] + [[package]] name = "fnv" version = "1.0.7" @@ -729,12 +708,14 @@ dependencies = [ ] [[package]] -name = "grounded" -version = "0.2.1" +name = "half" +version = "2.7.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5a7c71ebd5d467418b46639b622912cd0338ce59766bd19130bffcbf9ac6df2c" +checksum = "6ea2d84b969582b4b1864a92dc5d27cd2b77b622a8d79306834f1be5ba20d84b" dependencies = [ - "portable-atomic", + "cfg-if", + "crunchy", + "zerocopy", ] [[package]] @@ -746,12 +727,6 @@ dependencies = [ "byteorder", ] -[[package]] -name = "hashbrown" -version = "0.17.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4f467dd6dccf739c208452f8014c75c18bb8301b050ad1cfb27153803edb0f51" - [[package]] name = "heapless" version = "0.8.0" @@ -784,16 +759,6 @@ version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39" -[[package]] -name = "indexmap" -version = "2.14.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9" -dependencies = [ - "equivalent", - "hashbrown", -] - [[package]] name = "lazy_static" version = "1.5.0" @@ -831,22 +796,6 @@ dependencies = [ "tracing-subscriber", ] -[[package]] -name = "maitake-sync" -version = "0.3.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3d77c365d697828821727b9bc09e6bc3c518b8c63804e79e1be5a5ae091a7c5f" -dependencies = [ - "cordyceps", - "critical-section", - "loom", - "mutex-traits", - "mycelium-bitfield", - "pin-project", - "portable-atomic", - "tracing", -] - [[package]] name = "matchers" version = "0.2.0" @@ -871,22 +820,21 @@ dependencies = [ ] [[package]] -name = "memchr" -version = "2.8.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79" - -[[package]] -name = "mutex-traits" -version = "1.0.1" +name = "mec17xx-pac" +version = "0.1.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3929f2b5633d29cf7b6624992e5f3c1e9334f1193423e12d17be4faf678cde3f" +checksum = "5f21dce65d8af922b93d08336f6450629f51d1d1c7561ffe01b7cac4e735192d" +dependencies = [ + "cortex-m", + "cortex-m-rt", + "defmt 1.0.1", +] [[package]] -name = "mycelium-bitfield" -version = "0.1.5" +name = "memchr" +version = "2.8.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "24e0cc5e2c585acbd15c5ce911dff71e1f4d5313f43345873311c4f5efd741cc" +checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79" [[package]] name = "nb" @@ -942,17 +890,6 @@ dependencies = [ "syn", ] -[[package]] -name = "nxp-pac" -version = "0.1.0" -source = "git+https://github.com/embassy-rs/nxp-pac.git?rev=de562468e3956108913453f7a049d5fe7758de0b#de562468e3956108913453f7a049d5fe7758de0b" -dependencies = [ - "cfg_aliases", - "cortex-m", - "cortex-m-rt", - "defmt 0.3.100", -] - [[package]] name = "odp-service-common" version = "0.1.0" @@ -984,26 +921,6 @@ version = "1.0.15" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a" -[[package]] -name = "pin-project" -version = "1.1.12" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "cbf0d9e68100b3a7989b4901972f265cd542e560a3a8a724e1e20322f4d06ce9" -dependencies = [ - "pin-project-internal", -] - -[[package]] -name = "pin-project-internal" -version = "1.1.12" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a990e22f43e84855daf260dded30524ef4a9021cc7541c26540500a50b624389" -dependencies = [ - "proc-macro2", - "quote", - "syn", -] - [[package]] name = "pin-project-lite" version = "0.2.17" @@ -1047,9 +964,6 @@ name = "portable-atomic" version = "1.13.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "c33a9471896f1c69cecef8d20cbe2f7accd12527ce60845ff44c153bb2a21b49" -dependencies = [ - "critical-section", -] [[package]] name = "power-policy-interface" @@ -1104,36 +1018,6 @@ dependencies = [ "proc-macro2", ] -[[package]] -name = "rand_core" -version = "0.6.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c" - -[[package]] -name = "rand_core" -version = "0.9.5" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c" - -[[package]] -name = "rand_core" -version = "0.10.1" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "63b8176103e19a2643978565ca18b50549f6101881c443590420e4dc998a3c69" - -[[package]] -name = "regex" -version = "1.12.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e10754a14b9137dd7b1e3e5b0493cc9171fdd105e0ab477f51b72e7f3ac0e276" -dependencies = [ - "aho-corasick", - "memchr", - "regex-automata", - "regex-syntax", -] - [[package]] name = "regex-automata" version = "0.4.14" @@ -1467,6 +1351,12 @@ dependencies = [ "tracing-log", ] +[[package]] +name = "typenum" +version = "1.20.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "40ce102ab67701b8526c123c1bab5cbe42d7040ccfd0f64af1a385808d2f43de" + [[package]] name = "uart-service" version = "0.1.0" @@ -1485,12 +1375,6 @@ version = "1.0.24" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75" -[[package]] -name = "unicode-segmentation" -version = "1.13.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9629274872b2bfaf8d66f5f15725007f635594914870f65218920345aa11aa8c" - [[package]] name = "uuid" version = "1.17.0" diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs index c01cc58..7ff414c 100644 --- a/platform/dev-mec1723/src/board.rs +++ b/platform/dev-mec1723/src/board.rs @@ -1,45 +1,29 @@ -use embassy_mcxa::{bind_interrupts, clocks::periph_helpers::LpuartClockSel, lpuart}; use platform_common::board::BoardIo; -use static_cell::ConstStaticCell; +use embassy_microchip::{uart, bind_interrupts, peripherals, Peripherals}; bind_interrupts!(struct Irqs { - LPUART2 => lpuart::BbqInterruptHandler::; + UART0 => uart::InterruptHandler::; }); -const SIZE: usize = 4096; -static RX_BUF: ConstStaticCell<[u8; SIZE]> = ConstStaticCell::new([0u8; SIZE]); -static TX_BUF: ConstStaticCell<[u8; SIZE]> = ConstStaticCell::new([0u8; SIZE]); -/// Board IO for the dev-mcxa platform. -/// -/// This minimal development board provides a UART interface -/// for ODP service communication. +/// Board IO for the dev-mec1723 platform. pub struct Board { - /// UART for ODP service communication. - pub uart: lpuart::LpuartBbq, + pub uart: uart::Uart<'static, uart::Async>, } impl BoardIo for Board { - type Peripherals = embassy_mcxa::Peripherals; + type Peripherals = Peripherals; fn init(p: Self::Peripherals) -> Self { - let mut config = lpuart::BbqConfig::default(); - config.power = embassy_mcxa::clocks::PoweredClock::NormalEnabledDeepSleepDisabled; - config.source = LpuartClockSel::FroHfDiv; - - let tx_buf = TX_BUF.take(); - let rx_buf = RX_BUF.take(); - - // Create UART instance with DMA channels - let tx_dma = embassy_mcxa::dma::DmaChannel::new(p.DMA0_CH0); - let rx_dma = embassy_mcxa::dma::DmaChannel::new(p.DMA0_CH1); - - let parts = lpuart::BbqParts::new(p.LPUART2, Irqs, p.P2_2, tx_buf, tx_dma, p.P2_3, rx_buf, rx_dma) - .expect("failed to create BbqParts"); - - let lpuart = lpuart::LpuartBbq::new(parts, config, lpuart::BbqRxMode::Efficiency) - .expect("failed to initialize async LPUART"); - - Board { uart: lpuart } + Board { + /* Set up async UART on UART0 */ + uart: uart::Uart::new_async( + p.UART0, + p.GPIO105, + p.GPIO104, + Irqs, + uart::Config::default() + ).expect("Failed to create 'uart' in 'Board'.") + } } } diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs index 0dfac52..49b3533 100644 --- a/platform/dev-mec1723/src/main.rs +++ b/platform/dev-mec1723/src/main.rs @@ -8,14 +8,14 @@ use board::Board; use defmt::info; use defmt_rtt as _; use embassy_executor::Spawner; -use embassy_mcxa::lpuart; +use embassy_microchip::uart; use panic_probe as _; use platform_common::board::BoardIo; use platform_common::mock::MockOdpRelayHandler; use static_cell::StaticCell; #[embassy_executor::task] -async fn uart_service(uart: lpuart::LpuartBbq, relay: MockOdpRelayHandler) { +async fn uart_service(uart: uart::Uart<>, relay: MockOdpRelayHandler) { info!("Starting uart service"); static UART_SERVICE: StaticCell> = StaticCell::new(); let uart_service = uart_service::Service::new(relay).unwrap(); diff --git a/platform/dev-mec1723/supply-chain/audits.toml b/platform/dev-mec1723/supply-chain/audits.toml deleted file mode 100644 index 4f470da..0000000 --- a/platform/dev-mec1723/supply-chain/audits.toml +++ /dev/null @@ -1,79 +0,0 @@ - -# cargo-vet audits file - -[[audits.embassy-embedded-hal]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.6.0 -> 0.6.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: Cargo.toml dep version bump only (embassy-hal-internal 0.4.0->0.5.0). No code changes, no unsafe. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-executor]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.10.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.10.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: added armv8r target, dep version bumps, doc comment fixes. No new unsafe, no new imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-executor-macros]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.8.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.8.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: proc macro hygiene fix — renamed POOL_SIZE to __POOL_SIZE to avoid name collisions. No new unsafe, generated code unchanged. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-executor-timer-queue]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.1.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.1.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: changelog fix and edition 2021->2024. No code changes, no unsafe. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-futures]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.1.2 -> 0.1.2@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: edition 2021->2024, explicit feature declarations. No code changes, no unsafe. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-hal-internal]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.5.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.5.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: new aligned.rs module (4 transmute calls, all behind alignment assertions — sound), ring buffer Reader/Writer iterators (3 unsafe blocks for slice::from_raw_parts_mut and ptr reborrow — consistent with existing invariants). No new powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-mcxa]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -version = "0.1.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Co-owned by ODP, trusted publisher (Dirbaio from Embedded WG). Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-sync]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.8.0 -> 0.8.0@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: new rpc_service module (type-erased FnOnce dispatch, well-documented unsafe with clear invariants), OnceLock memory ordering fix (Relaxed->Acquire/Release), priority_channel bug fix, pubsub Send/Sync wrappers with proper bounds, pipe try_write_all. No new powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-time]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.5.1@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.5.1@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: added 62.5MHz tick rate, replaced custom div_ceil with u64::div_ceil, added core::error::Error impl for TimeoutError. No new unsafe, removed redundant helper fn. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-time-driver]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.2.2 -> 0.2.2@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "Delta: added 62.5MHz tick rate feature flag. No unsafe, no new imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.embassy-time-queue-utils]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -delta = "0.3.2@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a -> 0.3.2@git:bef4118731ac69092bee4489240f59c89af0d944" -importable = false -notes = "No diff between crates.io and git versions — identical source. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" diff --git a/platform/dev-mec1723/supply-chain/config.toml b/platform/dev-mec1723/supply-chain/config.toml deleted file mode 100644 index b0da212..0000000 --- a/platform/dev-mec1723/supply-chain/config.toml +++ /dev/null @@ -1,358 +0,0 @@ - -# cargo-vet config file - -[cargo-vet] -version = "0.10" - -[imports.bytecode-alliance] -url = "https://raw.githubusercontent.com/bytecodealliance/wasmtime/main/supply-chain/audits.toml" - -[imports.google] -url = "https://raw.githubusercontent.com/google/rust-crate-audits/main/audits.toml" - -[imports.mozilla] -url = "https://raw.githubusercontent.com/mozilla/supply-chain/main/audits.toml" - -[imports.open-device-partnership] -url = "https://raw.githubusercontent.com/OpenDevicePartnership/embedded-services/main/supply-chain/audits.toml" - -[policy.embassy-embedded-hal] -audit-as-crates-io = true - -[policy.embassy-executor] -audit-as-crates-io = true - -[policy.embassy-executor-macros] -audit-as-crates-io = true - -[policy.embassy-executor-timer-queue] -audit-as-crates-io = true - -[policy.embassy-futures] -audit-as-crates-io = true - -[policy.embassy-hal-internal] -audit-as-crates-io = true - -[policy.embassy-mcxa] -audit-as-crates-io = true - -[policy.embassy-sync] -audit-as-crates-io = true - -[policy.embassy-time] -audit-as-crates-io = true - -[policy.embassy-time-driver] -audit-as-crates-io = true - -[policy.embassy-time-queue-utils] -audit-as-crates-io = true - -[[exemptions.aho-corasick]] -version = "1.1.4" -criteria = "safe-to-deploy" - -[[exemptions.bare-metal]] -version = "0.2.5" -criteria = "safe-to-deploy" - -[[exemptions.bbqueue]] -version = "0.7.0" -criteria = "safe-to-deploy" - -[[exemptions.bitfield]] -version = "0.13.2" -criteria = "safe-to-deploy" - -[[exemptions.bq40z50-rx]] -version = "0.8.1" -criteria = "safe-to-deploy" - -[[exemptions.cc]] -version = "1.2.61" -criteria = "safe-to-deploy" - -[[exemptions.cfg-if]] -version = "1.0.4" -criteria = "safe-to-deploy" - -[[exemptions.cfg_aliases]] -version = "0.2.1" -criteria = "safe-to-deploy" - -[[exemptions.convert_case]] -version = "0.11.0" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m]] -version = "0.7.7" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m-rt]] -version = "0.7.5" -criteria = "safe-to-deploy" - -[[exemptions.cortex-m-rt-macros]] -version = "0.7.5" -criteria = "safe-to-deploy" - -[[exemptions.critical-section]] -version = "1.2.0" -criteria = "safe-to-deploy" - -[[exemptions.darling]] -version = "0.20.11" -criteria = "safe-to-deploy" - -[[exemptions.darling_core]] -version = "0.20.11" -criteria = "safe-to-deploy" - -[[exemptions.darling_macro]] -version = "0.20.11" -criteria = "safe-to-deploy" - -[[exemptions.defmt]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.defmt-macros]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.defmt-parser]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.defmt-rtt]] -version = "1.1.0" -criteria = "safe-to-deploy" - -[[exemptions.document-features]] -version = "0.2.12" -criteria = "safe-to-deploy" - -[[exemptions.embassy-executor]] -version = "0.10.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" -criteria = "safe-to-deploy" - -[[exemptions.embassy-executor-macros]] -version = "0.8.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" -criteria = "safe-to-deploy" - -[[exemptions.embassy-executor-timer-queue]] -version = "0.1.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" -criteria = "safe-to-deploy" - -[[exemptions.embassy-hal-internal]] -version = "0.5.0@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" -criteria = "safe-to-deploy" - -[[exemptions.embassy-time]] -version = "0.5.1@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" -criteria = "safe-to-deploy" - -[[exemptions.embassy-time-queue-utils]] -version = "0.3.2@git:7af7d3d270f019ff70f919c62c78d51f28f2d50a" -criteria = "safe-to-deploy" - -[[exemptions.embedded-hal]] -version = "0.2.7" -criteria = "safe-to-deploy" - -[[exemptions.embedded-sensors-hal]] -version = "0.1.1" -criteria = "safe-to-deploy" - -[[exemptions.find-msvc-tools]] -version = "0.1.9" -criteria = "safe-to-deploy" - -[[exemptions.futures-core]] -version = "0.3.32" -criteria = "safe-to-deploy" - -[[exemptions.futures-sink]] -version = "0.3.32" -criteria = "safe-to-deploy" - -[[exemptions.generator]] -version = "0.8.8" -criteria = "safe-to-deploy" - -[[exemptions.grounded]] -version = "0.2.1" -criteria = "safe-to-deploy" - -[[exemptions.hashbrown]] -version = "0.17.0" -criteria = "safe-to-deploy" - -[[exemptions.heapless]] -version = "0.9.3" -criteria = "safe-to-deploy" - -[[exemptions.ident_case]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.indexmap]] -version = "2.14.0" -criteria = "safe-to-deploy" - -[[exemptions.libc]] -version = "0.2.186" -criteria = "safe-to-deploy" - -[[exemptions.litrs]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.loom]] -version = "0.7.2" -criteria = "safe-to-deploy" - -[[exemptions.maitake-sync]] -version = "0.3.0" -criteria = "safe-to-deploy" - -[[exemptions.memchr]] -version = "2.8.0" -criteria = "safe-to-deploy" - -[[exemptions.once_cell]] -version = "1.21.4" -criteria = "safe-to-deploy" - -[[exemptions.panic-probe]] -version = "1.0.0" -criteria = "safe-to-deploy" - -[[exemptions.paste]] -version = "1.0.15" -criteria = "safe-to-deploy" - -[[exemptions.pin-project]] -version = "1.1.12" -criteria = "safe-to-deploy" - -[[exemptions.pin-project-internal]] -version = "1.1.12" -criteria = "safe-to-deploy" - -[[exemptions.pin-project-lite]] -version = "0.2.17" -criteria = "safe-to-deploy" - -[[exemptions.portable-atomic]] -version = "1.13.1" -criteria = "safe-to-deploy" - -[[exemptions.rand_core]] -version = "0.10.1" -criteria = "safe-to-deploy" - -[[exemptions.regex]] -version = "1.12.3" -criteria = "safe-to-deploy" - -[[exemptions.regex-automata]] -version = "0.4.14" -criteria = "safe-to-deploy" - -[[exemptions.regex-syntax]] -version = "0.8.10" -criteria = "safe-to-deploy" - -[[exemptions.rustc_version]] -version = "0.2.3" -criteria = "safe-to-deploy" - -[[exemptions.rustversion]] -version = "1.0.22" -criteria = "safe-to-deploy" - -[[exemptions.scoped-tls]] -version = "1.0.1" -criteria = "safe-to-deploy" - -[[exemptions.semver]] -version = "0.9.0" -criteria = "safe-to-deploy" - -[[exemptions.semver-parser]] -version = "0.7.0" -criteria = "safe-to-deploy" - -[[exemptions.stable_deref_trait]] -version = "1.2.1" -criteria = "safe-to-deploy" - -[[exemptions.subenum]] -version = "1.2.0" -criteria = "safe-to-deploy" - -[[exemptions.syn]] -version = "2.0.117" -criteria = "safe-to-deploy" - -[[exemptions.thiserror]] -version = "2.0.18" -criteria = "safe-to-deploy" - -[[exemptions.thiserror-impl]] -version = "2.0.18" -criteria = "safe-to-deploy" - -[[exemptions.tracing]] -version = "0.1.44" -criteria = "safe-to-deploy" - -[[exemptions.tracing-attributes]] -version = "0.1.31" -criteria = "safe-to-deploy" - -[[exemptions.tracing-core]] -version = "0.1.36" -criteria = "safe-to-deploy" - -[[exemptions.tracing-subscriber]] -version = "0.3.23" -criteria = "safe-to-deploy" - -[[exemptions.unicode-ident]] -version = "1.0.24" -criteria = "safe-to-deploy" - -[[exemptions.unicode-segmentation]] -version = "1.13.2" -criteria = "safe-to-deploy" - -[[exemptions.vcell]] -version = "0.1.3" -criteria = "safe-to-deploy" - -[[exemptions.volatile-register]] -version = "0.2.2" -criteria = "safe-to-deploy" - -[[exemptions.windows-link]] -version = "0.2.1" -criteria = "safe-to-deploy" - -[[exemptions.windows-result]] -version = "0.4.1" -criteria = "safe-to-deploy" - -[[exemptions.windows-sys]] -version = "0.61.2" -criteria = "safe-to-deploy" - -[[exemptions.zerocopy]] -version = "0.8.48" -criteria = "safe-to-deploy" - -[[exemptions.zerocopy-derive]] -version = "0.8.48" -criteria = "safe-to-deploy" diff --git a/platform/dev-mec1723/supply-chain/imports.lock b/platform/dev-mec1723/supply-chain/imports.lock deleted file mode 100644 index 5cbae2f..0000000 --- a/platform/dev-mec1723/supply-chain/imports.lock +++ /dev/null @@ -1,869 +0,0 @@ - -# cargo-vet imports lock - -[[audits.bytecode-alliance.audits.bitflags]] -who = "Jamey Sharp " -criteria = "safe-to-deploy" -delta = "2.1.0 -> 2.2.1" -notes = """ -This version adds unsafe impls of traits from the bytemuck crate when built -with that library enabled, but I believe the impls satisfy the documented -safety requirements for bytemuck. The other changes are minor. -""" - -[[audits.bytecode-alliance.audits.bitflags]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "2.3.2 -> 2.3.3" -notes = """ -Nothing outside the realm of what one would expect from a bitflags generator, -all as expected. -""" - -[[audits.bytecode-alliance.audits.bitflags]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "2.4.1 -> 2.6.0" -notes = """ -Changes in how macros are invoked and various bits and pieces of macro-fu. -Otherwise no major changes and nothing dealing with `unsafe`. -""" - -[[audits.bytecode-alliance.audits.bitflags]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "2.7.0 -> 2.9.4" -notes = "Tweaks to the macro, nothing out of order." - -[[audits.bytecode-alliance.audits.bitflags]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "2.10.0 -> 2.11.1" -notes = "Minor updates, nothing awry here." - -[[audits.bytecode-alliance.audits.embedded-io]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "0.4.0" -notes = "No `unsafe` code and only uses `std` in ways one would expect the crate to do so." - -[[audits.bytecode-alliance.audits.embedded-io]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.0 -> 0.6.1" -notes = "Major updates, but almost all safe code. Lots of pruning/deletions, nothing out of the ordrinary." - -[[audits.bytecode-alliance.audits.heck]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.4.1 -> 0.5.0" -notes = "Minor changes for a `no_std` upgrade but otherwise everything looks as expected." - -[[audits.bytecode-alliance.audits.matchers]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.1.0" - -[[audits.bytecode-alliance.audits.matchers]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.0 -> 0.2.0" -notes = "Some unsafe code, but not more than before. Nothing awry." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.46.0" -notes = "one use of unsafe to call windows specific api to get console handle." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.46.0 -> 0.50.1" -notes = "Lots of stylistic/rust-related changes, plus new features, but nothing out of the ordrinary." - -[[audits.bytecode-alliance.audits.nu-ansi-term]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.50.1 -> 0.50.3" -notes = "CI changes, Rust changes, nothing out of the ordinary." - -[[audits.bytecode-alliance.audits.num-traits]] -who = "Andrew Brown " -criteria = "safe-to-deploy" -version = "0.2.19" -notes = "As advertised: a numeric library. The only `unsafe` is from some float-to-int conversions, which seems expected." - -[[audits.bytecode-alliance.audits.sharded-slab]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "0.1.4" -notes = "I always really enjoy reading eliza's code, she left perfect comments at every use of unsafe." - -[[audits.bytecode-alliance.audits.shlex]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "1.1.0" -notes = "Only minor `unsafe` code blocks which look valid and otherwise does what it says on the tin." - -[[audits.bytecode-alliance.audits.smallvec]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "1.13.2 -> 1.14.0" -notes = "Minor new feature, nothing out of the ordinary." - -[[audits.bytecode-alliance.audits.static_assertions]] -who = "Andrew Brown " -criteria = "safe-to-deploy" -version = "1.1.0" -notes = "No dependencies and completely a compile-time crate as advertised. Uses `unsafe` in one module as a compile-time check only: `mem::transmute` and `ptr::write` are wrapped in an impossible-to-run closure." - -[[audits.bytecode-alliance.audits.thread_local]] -who = "Pat Hickey " -criteria = "safe-to-deploy" -version = "1.1.4" -notes = "uses unsafe to implement thread local storage of objects" - -[[audits.bytecode-alliance.audits.tracing-log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -version = "0.1.3" -notes = """ -This is a standard adapter between the `log` ecosystem and the `tracing` -ecosystem. There's one `unsafe` block in this crate and it's well-scoped. -""" - -[[audits.bytecode-alliance.audits.tracing-log]] -who = "Alex Crichton " -criteria = "safe-to-deploy" -delta = "0.1.3 -> 0.2.0" -notes = "Nothing out of the ordinary, a typical major version update and nothing awry." - -[[audits.google.audits.autocfg]] -who = "Manish Goregaokar " -criteria = "safe-to-deploy" -version = "1.4.0" -notes = "Contains no unsafe" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.bitflags]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.3.2" -notes = """ -Security review of earlier versions of the crate can be found at -(Google-internal, sorry): go/image-crate-chromium-security-review - -The crate exposes a function marked as `unsafe`, but doesn't use any -`unsafe` blocks (except for tests of the single `unsafe` function). I -think this justifies marking this crate as `ub-risk-1`. - -Additional review comments can be found at https://crrev.com/c/4723145/31 -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.byteorder]] -who = "danakj " -criteria = "safe-to-deploy" -version = "1.5.0" -notes = "Unsafe review in https://crrev.com/c/5838022" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.equivalent]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.1" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.equivalent]] -who = "Jonathan Hao " -criteria = "safe-to-deploy" -delta = "1.0.1 -> 1.0.2" -notes = "No changes to any .rs files or Rust code." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.heck]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "0.4.1" -notes = """ -Grepped for `-i cipher`, `-i crypto`, `'\bfs\b'``, `'\bnet\b'``, `'\bunsafe\b'`` -and there were no hits. - -`heck` (version `0.3.3`) has been added to Chromium in -https://source.chromium.org/chromium/chromium/src/+/28841c33c77833cc30b286f9ae24c97e7a8f4057 -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.lazy_static]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.4.0" -notes = ''' -I grepped for \"crypt\", \"cipher\", \"fs\", \"net\" - there were no hits. - -There are two places where `unsafe` is used. Unsafe review notes can be found -in https://crrev.com/c/5347418. - -This crate has been added to Chromium in https://crrev.com/c/3321895. -''' -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.lazy_static]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.4.0 -> 1.5.0" -notes = "Unsafe review notes: https://crrev.com/c/5650836" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.log]] -who = "danakj " -criteria = "safe-to-deploy" -version = "0.4.22" -notes = """ -Unsafe review in https://docs.google.com/document/d/1IXQbD1GhTRqNHIGxq6yy7qHqxeO4CwN5noMFXnqyDIM/edit?usp=sharing - -Unsafety is generally very well-documented, with one exception, which we -describe in the review doc. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.log]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "0.4.22 -> 0.4.25" -notes = "No impact on `unsafe` usage in `lib.rs`." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.log]] -who = "Daniel Cheng " -criteria = "safe-to-deploy" -delta = "0.4.25 -> 0.4.26" -notes = "Only trivial code and documentation changes." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -version = "1.0.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 0.1.3" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.nb]] -who = "George Burgess IV " -criteria = "safe-to-deploy" -delta = "1.0.0 -> 1.1.0" -aggregated-from = "https://chromium.googlesource.com/chromiumos/third_party/rust_crates/+/refs/heads/main/cargo-vet/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -version = "1.0.78" -notes = """ -Grepped for "crypt", "cipher", "fs", "net" - there were no hits -(except for a benign "fs" hit in a doc comment) - -Notes from the `unsafe` review can be found in https://crrev.com/c/5385745. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.0.78 -> 1.0.79" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Adrian Taylor " -criteria = "safe-to-deploy" -delta = "1.0.79 -> 1.0.80" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Dustin J. Mitchell " -criteria = "safe-to-deploy" -delta = "1.0.80 -> 1.0.81" -notes = "Comment changes only" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "danakj " -criteria = "safe-to-deploy" -delta = "1.0.81 -> 1.0.82" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Dustin J. Mitchell " -criteria = "safe-to-deploy" -delta = "1.0.82 -> 1.0.83" -notes = "Substantive change is replacing String with Box, saving memory." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.0.83 -> 1.0.84" -notes = "Only doc comment changes in `src/lib.rs`." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "danakj@chromium.org" -criteria = "safe-to-deploy" -delta = "1.0.84 -> 1.0.85" -notes = "Test-only changes." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Lukasz Anforowicz " -criteria = "safe-to-deploy" -delta = "1.0.85 -> 1.0.86" -notes = """ -Comment-only changes in `build.rs`. -Reordering of `Cargo.toml` entries. -Just bumping up the version number in `lib.rs`. -Config-related changes in `test_size.rs`. -""" -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "danakj " -criteria = "safe-to-deploy" -delta = "1.0.86 -> 1.0.87" -notes = "No new unsafe interactions." -aggregated-from = "https://chromium.googlesource.com/chromium/src/+/main/third_party/rust/chromium_crates_io/supply-chain/audits.toml?format=TEXT" - -[[audits.google.audits.proc-macro2]] -who = "Liza Burakova ", - "Erich Gubler ", -] -criteria = "safe-to-deploy" -delta = "2.6.0 -> 2.7.0" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.bitflags]] -who = "Benjamin VanderSloot " -criteria = "safe-to-deploy" -delta = "2.9.4 -> 2.10.0" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.fnv]] -who = "Bobby Holley " -criteria = "safe-to-deploy" -version = "1.0.7" -notes = "Simple hasher implementation with no unsafe code." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.log]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "0.4.26 -> 0.4.29" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.proc-macro-error-attr2]] -who = "Kagami Sascha Rosylight " -criteria = "safe-to-deploy" -version = "2.0.0" -notes = "No unsafe block." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.proc-macro-error2]] -who = "Kagami Sascha Rosylight " -criteria = "safe-to-deploy" -version = "2.0.1" -notes = "No unsafe block with a lovely `#![forbid(unsafe_code)]`." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.proc-macro2]] -who = "Jan-Erik Rediger " -criteria = "safe-to-deploy" -delta = "1.0.94 -> 1.0.106" -aggregated-from = "https://raw.githubusercontent.com/mozilla/glean/main/supply-chain/audits.toml" - -[[audits.mozilla.audits.quote]] -who = "Jan-Erik Rediger " -criteria = "safe-to-deploy" -delta = "1.0.40 -> 1.0.45" -aggregated-from = "https://raw.githubusercontent.com/mozilla/glean/main/supply-chain/audits.toml" - -[[audits.mozilla.audits.serde_core]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.0.226 -> 1.0.227" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.serde_core]] -who = "Jan-Erik Rediger " -criteria = "safe-to-deploy" -delta = "1.0.227 -> 1.0.228" -aggregated-from = "https://raw.githubusercontent.com/mozilla/glean/main/supply-chain/audits.toml" - -[[audits.mozilla.audits.sharded-slab]] -who = "Mark Hammond " -criteria = "safe-to-deploy" -delta = "0.1.4 -> 0.1.7" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.shlex]] -who = "Max Inden " -criteria = "safe-to-deploy" -delta = "1.1.0 -> 1.3.0" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.smallvec]] -who = "Erich Gubler " -criteria = "safe-to-deploy" -delta = "1.14.0 -> 1.15.1" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.strsim]] -who = "Ben Dean-Kawamura " -criteria = "safe-to-deploy" -delta = "0.10.0 -> 0.11.1" -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.mozilla.audits.void]] -who = "Bobby Holley " -criteria = "safe-to-deploy" -version = "1.0.2" -notes = "Very small crate, just hosts the Void type for easier cross-crate interfacing." -aggregated-from = "https://hg.mozilla.org/mozilla-central/raw-file/tip/supply-chain/audits.toml" - -[[audits.open-device-partnership.audits.autocfg]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "1.4.0 -> 1.5.0" -notes = "No unsafe, no build.rs, no network access; delta adds edition-aware rustc probing and best-effort probe-file cleanup only. Assisted-by: copilot-cli:GPT-5.3-Codex cargo-vet" - -[[audits.open-device-partnership.audits.bitfield]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.13.2 -> 0.15.0" -notes = "Delta audit: BitRange/Bit traits split into read-only and mutable variants (BitRangeMut/BitMut); added mask constant generation; clippy fixes; MSRV bump. No unsafe, no build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.bitfield]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.15.0 -> 0.17.0" -notes = "Delta: adds bitwise op derives, constructor derives, arbitrary visibility. Pure declarative macros. No unsafe, no build script. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.bitfield-struct]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.10.1" -notes = "Proc-macro crate generating safe bitfield structs. No unsafe, no build script. Standard proc-macro deps only. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.bitfield-struct]] -who = "matteotullo " -criteria = "safe-to-deploy" -delta = "0.10.1 -> 0.12.1" -notes = "Adds hash and bitenum derives, mostly parsing and refactoring changes. No code execution nor writing to the filesystem." - -[[audits.open-device-partnership.audits.const-init]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "1.0.0" - -[[audits.open-device-partnership.audits.cordyceps]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.3.4" -notes = "Intrusive data structures crate (no_std). ~115 unsafe blocks, all necessary for intrusive linked list/queue/stack ops. Correct patterns: addr_of_mut, proper atomic orderings, Vyukov MPSC algorithm. No build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.defmt]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.3.100" -notes = "Compatibility shim: no_std crate that re-exports defmt 1.x items for 0.3 API compatibility. No unsafe code, no build script, no powerful imports, no logic - pure pub-use re-exports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.device-driver]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "1.0.7" -notes = "no_std device driver toolkit. Unsafe limited to ops.rs bitfield load/store using get_unchecked with documented invariants; fuzz-tested against bitvec. No build script, no proc macros, no filesystem/network/process access. Assisted-by: copilot-chat:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.device-driver]] -who = "Adam Sasine " -criteria = "safe-to-deploy" -delta = "1.0.7 -> 1.0.9" -notes = "Fixes compilation bugs for large registers but does not change invariants or testing strategy." - -[[audits.open-device-partnership.audits.embassy-embedded-hal]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.5.0" -notes = "No unsafe, no build script, no proc macros. no_std shared bus/flash partition utilities for embedded-hal traits. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embassy-embedded-hal]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.5.0 -> 0.6.0" -notes = "No unsafe code, no build script, no powerful imports. Added Clone for I2C devices. Updated embassy dependencies (embassy-sync 0.7→0.8, embassy-hal-internal 0.3→0.4, embassy-time 0.5→0.5.1). All changes safe." - -[[audits.open-device-partnership.audits.embassy-futures]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.1.2" -notes = "no_std future combinators. All unsafe is pin-projection and no-op RawWaker - reviewed and sound. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embassy-sync]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.8.0" -notes = "no_std async sync primitives. Substantial unsafe for UnsafeCell-based interiors and Send/Sync impls -- all reviewed and sound, guarded by RawMutex/critical_section. Build script only reads TARGET env var. No proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embassy-time-driver]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.2.1" -notes = "no_std driver trait for embassy-time. Minimal unsafe for extern Rust FFI calls (sound via links key). Empty build.rs. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embassy-time-driver]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.2.1 -> 0.2.2" -notes = "Rust 2024 edition update with 375kHz tick rate feature. Empty build.rs, no unsafe code, no powerful imports." - -[[audits.open-device-partnership.audits.embedded-batteries]] -who = "matteotullo " -criteria = "safe-to-deploy" -version = "0.3.4" -notes = "ODP crates are always trusted." - -[[audits.open-device-partnership.audits.embedded-batteries-async]] -who = "matteotullo " -criteria = "safe-to-deploy" -version = "0.3.4" -notes = "ODP crates are always trusted." - -[[audits.open-device-partnership.audits.embedded-crc-macros]] -who = "Matteo Tullo " -criteria = "safe-to-deploy" -version = "1.0.0" - -[[audits.open-device-partnership.audits.embedded-fans]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -version = "0.1.0" -notes = "ODP crates are always trusted." - -[[audits.open-device-partnership.audits.embedded-fans-async]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -version = "0.2.0" -notes = "ODP crates are always trusted." - -[[audits.open-device-partnership.audits.embedded-hal]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.2.7 -> 1.0.0" -notes = "Pure no_std trait crate. Complete API redesign for 1.0: removed nb-based traits, CAN module, all unsafe code. Only defines traits/enums/types for digital, I2C, SPI, PWM, delay. No build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-hal-async]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "1.0.0" -notes = "no_std async HAL trait definitions. No unsafe in library. Build script only runs rustc --version. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-hal-nb]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "1.0.0" -notes = "no_std trait-only crate. No unsafe, no build script, no proc macros, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-io]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.6.1 -> 0.7.1" -notes = "No unsafe, no build script, no I/O. Trait evolution: Error requires core::error::Error (MSRV 1.81), BufRead: Read, Seek gains seek_relative, new VecDeque impls, defmt bumped to v1. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-io-async]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.6.1" -notes = "No unsafe. Build script only detects nightly via rustc --version. Pure async trait definitions for embedded I/O. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-io-async]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.6.1 -> 0.7.0" -notes = "Delta 0.6.1->0.7.0: No unsafe. Build script removed (AFIT now stable). flush() made required, BufRead requires Read, new VecDeque impls. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-mcu-hal]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.2.0" -notes = "Trait-based MCU HAL with zero unsafe code. No build script or powerful imports. Pure trait design with optional chrono/defmt features. Ideal for embedded controllers." - -[[audits.open-device-partnership.audits.embedded-sensors-hal-async]] -who = "Kurtis Dinelle " -criteria = "safe-to-deploy" -version = "0.3.0" -notes = "ODP crates are always trusted." - -[[audits.open-device-partnership.audits.embedded-storage]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.3.1" -notes = "Pure no_std storage abstraction traits. deny(unsafe_code), no build script, no dependencies, no powerful imports. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.embedded-storage-async]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.4.1" -notes = "Pure no_std async trait definitions for NOR flash storage. No unsafe code, no build script, no powerful imports. Only dependency is embedded-storage. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.hash32]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.3.1" -notes = "no_std 32-bit hashing (FNV, MurmurHash3). ~10 unsafe blocks in murmur3.rs for MaybeUninit buffer handling - all sound. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.heapless]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.8.0" -notes = "no_std fixed-capacity data structures. Extensive unsafe for MaybeUninit buffer management, lock-free queues (Vyukov MPMC, SPSC), and Treiber stack memory pools with ABA prevention. Patterns mirror std or published algorithms. Build script probes for atomic/LLSC support. Assisted-by: copilot-cli:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.mutex-traits]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "1.0.1" - -[[audits.open-device-partnership.audits.mycelium-bitfield]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.1.5" -notes = "Pure safe no_std bitfield macro crate. No unsafe code, no build script, no proc macros, no dependencies, no powerful imports. Only core:: types used. Assisted-by: copilot-chat:claude-opus-4.6 cargo-vet" - -[[audits.open-device-partnership.audits.num_enum]] -who = "Matteo Tullo " -criteria = "safe-to-deploy" -version = "0.7.4" - -[[audits.open-device-partnership.audits.num_enum]] -who = "Billy Price " -criteria = "safe-to-deploy" -delta = "0.7.4 -> 0.7.5" -notes = "Looks like this is just uptaking a new version of num_enum_derive" - -[[audits.open-device-partnership.audits.num_enum]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.7.5 -> 0.7.6" -notes = "Version bump with test infrastructure updates. No unsafe code, no build script, no powerful imports. Purely additive test changes." - -[[audits.open-device-partnership.audits.num_enum_derive]] -who = "Matteo Tullo " -criteria = "safe-to-deploy" -version = "0.7.4" - -[[audits.open-device-partnership.audits.num_enum_derive]] -who = "Billy Price " -criteria = "safe-to-deploy" -delta = "0.7.4 -> 0.7.5" -notes = "Looks like mostly improvements to error messaging" - -[[audits.open-device-partnership.audits.num_enum_derive]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "0.7.5 -> 0.7.6" -notes = "Minor update adding byte literal support for enum discriminants. No unsafe code, no build script, no powerful imports." - -[[audits.open-device-partnership.audits.rand_core]] -who = "Billy Price " -criteria = "safe-to-deploy" -delta = "0.6.4 -> 0.9.5" - -[[audits.open-device-partnership.audits.serde]] -who = "Robert Zieba " -criteria = "safe-to-deploy" -version = "1.0.228" -notes = "Changes are mostly a reorganization of the internal module structure" - -[[audits.open-device-partnership.audits.serde_core]] -who = "Robert Zieba " -criteria = "safe-to-deploy" -version = "1.0.226" - -[[audits.open-device-partnership.audits.serde_derive]] -who = "Robert Zieba " -criteria = "safe-to-deploy" -version = "1.0.228" -notes = "Diff is clean-up in proc macros" - -[[audits.open-device-partnership.audits.smbus-pec]] -who = "Matteo Tullo " -criteria = "safe-to-deploy" -version = "1.0.1" - -[[audits.open-device-partnership.audits.static_cell]] -who = "Robert Zieba " -criteria = "safe-to-deploy" -version = "2.1.1" - -[[audits.open-device-partnership.audits.thread_local]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -delta = "1.1.4 -> 1.1.9" -notes = "No build script, no FS/net/process capability expansion; unsafe refactor to lock-free insertion and nightly TLS path appears sound on review. Assisted-by: copilot-cli:GPT-5.3-Codex cargo-vet" - -[[audits.open-device-partnership.audits.uuid]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "1.17.0" - -[[audits.open-device-partnership.audits.valuable]] -who = "Jerry Xie " -criteria = "safe-to-deploy" -version = "0.1.1" -notes = "No unsafe code; build.rs only sets target atomic cfg via env; no fs/net/process capability use observed; behavior matches value-inspection purpose. Assisted-by: copilot-cli:GPT-5.3-Codex cargo-vet" From 126c56bc29c3dc420b2316eaee1457f33043fa27 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 16:31:29 -0700 Subject: [PATCH 03/15] compiled successfully --- platform/dev-mec1723/src/clocks.rs | 56 ------------------------------ platform/dev-mec1723/src/main.rs | 9 ++--- 2 files changed, 3 insertions(+), 62 deletions(-) delete mode 100644 platform/dev-mec1723/src/clocks.rs diff --git a/platform/dev-mec1723/src/clocks.rs b/platform/dev-mec1723/src/clocks.rs deleted file mode 100644 index 1fc0469..0000000 --- a/platform/dev-mec1723/src/clocks.rs +++ /dev/null @@ -1,56 +0,0 @@ -//! Clock configuration for the MCXA dev board. - -use embassy_mcxa::clocks::PoweredClock; -use embassy_mcxa::clocks::config::{ - ClocksConfig, CoreSleep, Div8, FircConfig, FircFreqSel, FlashSleep, MainClockConfig, MainClockSource, - VddDriveStrength, VddLevel, -}; - -/// Build the desired clock tree configuration for the board. -pub fn config() -> ClocksConfig { - let mut cfg = ClocksConfig::default(); - - // Enable 180MHz clock source - let mut fcfg = FircConfig::default(); - fcfg.frequency = FircFreqSel::Mhz180; - fcfg.power = PoweredClock::NormalEnabledDeepSleepDisabled; - fcfg.fro_hf_enabled = true; - fcfg.clk_hf_fundamental_enabled = false; - fcfg.fro_hf_div = Some(const { Div8::from_divisor(4).unwrap() }); - cfg.firc = Some(fcfg); - - // Enable 12M osc - cfg.sirc.fro_12m_enabled = true; - cfg.sirc.fro_lf_div = Some(Div8::no_div()); - cfg.sirc.power = PoweredClock::AlwaysEnabled; - - // Disable 16K osc - cfg.fro16k = None; - - // Disable external osc - cfg.sosc = None; - - // Disable PLL - cfg.spll = None; - - // Feed core from 180M osc - cfg.main_clock = MainClockConfig { - source: MainClockSource::FircHfRoot, - power: PoweredClock::NormalEnabledDeepSleepDisabled, - ahb_clk_div: Div8::no_div(), - }; - - // We don't sleep, set relatively high power - cfg.vdd_power.active_mode.level = VddLevel::OverDriveMode; - cfg.vdd_power.low_power_mode.level = VddLevel::MidDriveMode; - cfg.vdd_power.active_mode.drive = VddDriveStrength::Normal; - cfg.vdd_power.low_power_mode.drive = VddDriveStrength::Low { enable_bandgap: false }; - - // Set "never sleep" mode - cfg.vdd_power.core_sleep = CoreSleep::WfeUngated; - - // Set flash doze, allowing internal flash clocks to be gated on sleep - cfg.vdd_power.flash_sleep = FlashSleep::FlashDoze; - - cfg -} diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs index 49b3533..e3b747d 100644 --- a/platform/dev-mec1723/src/main.rs +++ b/platform/dev-mec1723/src/main.rs @@ -2,7 +2,6 @@ #![no_main] mod board; -mod clocks; use board::Board; use defmt::info; @@ -15,7 +14,7 @@ use platform_common::mock::MockOdpRelayHandler; use static_cell::StaticCell; #[embassy_executor::task] -async fn uart_service(uart: uart::Uart<>, relay: MockOdpRelayHandler) { +async fn uart_service(uart: uart::Uart<'static, uart::Async>, relay: MockOdpRelayHandler) { info!("Starting uart service"); static UART_SERVICE: StaticCell> = StaticCell::new(); let uart_service = uart_service::Service::new(relay).unwrap(); @@ -27,12 +26,10 @@ async fn uart_service(uart: uart::Uart<>, relay: MockOdpRelayHandler) { #[embassy_executor::main] async fn main(spawner: Spawner) { - let mut cfg = embassy_mcxa::config::Config::default(); - cfg.clock_cfg = clocks::config(); - let p = embassy_mcxa::init(cfg); + let p = embassy_microchip::init(embassy_microchip::config::Config::default()); let board = Board::init(p); - info!("Hello world from MCXA!"); + info!("Hello world from MEC1723!"); let relay = platform_common::mock::init(spawner).await; spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); From 48ed5a329a05fe3913554ceaded8c3a32ccb3d18 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 16:34:18 -0700 Subject: [PATCH 04/15] fixed comments in memory.x --- platform/dev-mec1723/memory.x | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/platform/dev-mec1723/memory.x b/platform/dev-mec1723/memory.x index b4c3aad..3d94b2a 100644 --- a/platform/dev-mec1723/memory.x +++ b/platform/dev-mec1723/memory.x @@ -1,11 +1,11 @@ -// Datasheet for the chip: https://www.microchip.com/content/dam/mchp/documents/CPG/ProductDocuments/DataSheets/MEC172x-Data-Sheet-DS00003583E.pdf - MEMORY { - - // u_Notes about FLASH: - // - This assumes the 'Cache SPI Enable' bit is 0, which it is by default. - // - See FIGURE 7-1 on page 180 of the datasheet for more info (384KB comes from 32KB + 352KB. If the 'Cache SPI Enable' bit was 1, FLASH would just be 352KB). - // - Also, the 384K number is supported by https://github.com/embassy-rs/embassy/blob/e9c32931b906649d65fc502fe8e8f2c70ef1e6ab/examples/microchip/memory.x + /* + u_Notes about FLASH: + - This assumes the 'Cache SPI Enable' bit is 0, which it is by default. + - See FIGURE 7-1 on page 180 of the datasheet for more info (384KB comes from 32KB + 352KB. If the 'Cache SPI Enable' bit was 1, FLASH would just be 352KB). + - ^^ Datasheet for the chip: https://www.microchip.com/content/dam/mchp/documents/CPG/ProductDocuments/DataSheets/MEC172x-Data-Sheet-DS00003583E.pdf + - Also, the 384K number is supported by https://github.com/embassy-rs/embassy/blob/e9c32931b906649d65fc502fe8e8f2c70ef1e6ab/examples/microchip/memory.x + */ FLASH : ORIGIN = 0x000C0000, LENGTH = 384K RAM : ORIGIN = 0x00118000, LENGTH = 62K From 9e4d4c73b370ce043d72d35e950eb4fe52a63aab Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 16:39:34 -0700 Subject: [PATCH 05/15] updated config.toml --- platform/dev-mec1723/.cargo/config.toml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml index c2d2d53..b53d797 100644 --- a/platform/dev-mec1723/.cargo/config.toml +++ b/platform/dev-mec1723/.cargo/config.toml @@ -1,5 +1,5 @@ -[target.thumbv8m.main-none-eabihf] -runner = 'probe-rs run --chip MCXA276 --preverify --verify --protocol swd --speed 12000' +[target.thumbv7em-none-eabihf] +runner = 'probe-rs run --chip MEC1723N_B0_SZ --preverify --verify --protocol swd --speed 12000' rustflags = [ "-C", @@ -15,7 +15,7 @@ rustflags = [ ] [build] -target = "thumbv8m.main-none-eabihf" # Cortex-M33 +target = "thumbv7em-none-eabihf" [env] DEFMT_LOG = "trace" From a5f6da56783982bcd6f8a936e75f8b3aebef3220 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 17:24:28 -0700 Subject: [PATCH 06/15] j-link issue --- platform/dev-mec1723/.cargo/config.toml | 2 +- platform/dev-mec1723/src/board.rs | 1 + platform/dev-mec1723/src/main.rs | 40 ++++++++++++++++++------- 3 files changed, 32 insertions(+), 11 deletions(-) diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml index b53d797..25f1538 100644 --- a/platform/dev-mec1723/.cargo/config.toml +++ b/platform/dev-mec1723/.cargo/config.toml @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = 'probe-rs run --chip MEC1723N_B0_SZ --preverify --verify --protocol swd --speed 12000' +runner = 'probe-rs run --chip MEC1723N_B0_SZ --protocol swd --speed 4000' rustflags = [ "-C", diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs index 7ff414c..01b5715 100644 --- a/platform/dev-mec1723/src/board.rs +++ b/platform/dev-mec1723/src/board.rs @@ -7,6 +7,7 @@ bind_interrupts!(struct Irqs { /// Board IO for the dev-mec1723 platform. +#[allow(dead_code)] pub struct Board { pub uart: uart::Uart<'static, uart::Async>, } diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs index e3b747d..b2698ba 100644 --- a/platform/dev-mec1723/src/main.rs +++ b/platform/dev-mec1723/src/main.rs @@ -3,13 +3,13 @@ mod board; -use board::Board; +//use board::Board; use defmt::info; use defmt_rtt as _; use embassy_executor::Spawner; use embassy_microchip::uart; use panic_probe as _; -use platform_common::board::BoardIo; +//use platform_common::board::BoardIo; use platform_common::mock::MockOdpRelayHandler; use static_cell::StaticCell; @@ -24,13 +24,33 @@ async fn uart_service(uart: uart::Uart<'static, uart::Async>, relay: MockOdpRela panic!("uart-service error: {:?}", e); } -#[embassy_executor::main] -async fn main(spawner: Spawner) { - let p = embassy_microchip::init(embassy_microchip::config::Config::default()); - let board = Board::init(p); +// #[embassy_executor::main] +// async fn main(spawner: Spawner) { +// info!("Booting..."); +// let p = embassy_microchip::init(embassy_microchip::config::Config::default()); +// let board = Board::init(p); - info!("Hello world from MEC1723!"); +// info!("Hello world from MEC1723!"); - let relay = platform_common::mock::init(spawner).await; - spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); -} +// let relay = platform_common::mock::init(spawner).await; +// spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); +// } + +use embassy_microchip::gpio::{Level, Output}; + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::info!("RTT initialized!"); + + let p = embassy_microchip::init(embassy_microchip::config::Config::default()); + + // Replace with actual LED GPIO from your board schematic + let mut led = Output::new(p.GPIO153, Level::Low); // example pin + + loop { + led.set_high(); + cortex_m::asm::delay(10_000_000); + led.set_low(); + cortex_m::asm::delay(10_000_000); + } +} \ No newline at end of file From cf87067488a07e5d0d47f3aaafd3c6d0e9cdcf68 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 17:54:17 -0700 Subject: [PATCH 07/15] rtt works --- platform/dev-mec1723/.cargo/config.toml | 2 +- platform/dev-mec1723/Embed.toml | 16 + platform/dev-mec1723/debug.log | 1127 ++++++++++++++++++++++ platform/dev-mec1723/mec1723_custom.yaml | 46 + platform/dev-mec1723/src/board.rs | 1 - platform/dev-mec1723/src/main.rs | 39 +- 6 files changed, 1200 insertions(+), 31 deletions(-) create mode 100644 platform/dev-mec1723/Embed.toml create mode 100644 platform/dev-mec1723/debug.log create mode 100644 platform/dev-mec1723/mec1723_custom.yaml diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml index 25f1538..79fd310 100644 --- a/platform/dev-mec1723/.cargo/config.toml +++ b/platform/dev-mec1723/.cargo/config.toml @@ -1,5 +1,5 @@ [target.thumbv7em-none-eabihf] -runner = 'probe-rs run --chip MEC1723N_B0_SZ --protocol swd --speed 4000' +runner = 'probe-rs run --chip-description-path mec1723_custom.yaml --chip MEC1723N_B0_SZ_CUSTOM --protocol swd --speed 4000' rustflags = [ "-C", diff --git a/platform/dev-mec1723/Embed.toml b/platform/dev-mec1723/Embed.toml new file mode 100644 index 0000000..2b1a6a6 --- /dev/null +++ b/platform/dev-mec1723/Embed.toml @@ -0,0 +1,16 @@ +[default.general] +chip = "MEC1723N_B0_SZ" + +[default.rtt] +enabled = true +timeout = 5000 + +[default.probe] +protocol = "Swd" +speed = 4000 + +[default.flashing] +enabled = true + +[default.reset] +halt_afterwards = false \ No newline at end of file diff --git a/platform/dev-mec1723/debug.log b/platform/dev-mec1723/debug.log new file mode 100644 index 0000000..2dada00 --- /dev/null +++ b/platform/dev-mec1723/debug.log @@ -0,0 +1,1127 @@ + Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.08s + Running `probe-rs run --chip MEC1723N_B0_SZ --protocol swd --speed 4000 target/thumbv7em-none-eabihf/debug/dev-mec1723` +DEBUG probe_rs::cmd::run: No .embedded_test linker section in ELF +DEBUG probe_rs::cmd::run: No embedded-test in ELF file. Running as normal +DEBUG list_cmsisdap_devices: probe_rs::probe::cmsisdap::tools: Searching for CMSIS-DAP probes using nusb +DEBUG list_cmsisdap_devices: probe_rs::probe::cmsisdap::tools: Found 0 CMSIS-DAP probes using nusb, searching HID +DEBUG list_cmsisdap_devices: probe_rs::probe::cmsisdap::tools: Found 0 CMSIS-DAP probes total +DEBUG list_wlink_devices: probe_rs::probe::wlink: Searching for WCH-Link(RV) probes +DEBUG list_wlink_devices: probe_rs::probe::wlink: Found 0 WCH-Link probes total +DEBUG probe_rs::config::registry: Searching registry for chip with name MEC1723N_B0_SZ +DEBUG probe_rs::config::registry: Exact match for chip name: MEC1723N_B0_SZ + INFO probe_rs::config::target: Using sequence Arm(Mec172x) +DEBUG probe_rs::probe::cmsisdap::tools: Attempting to open 1366:1020 in CMSIS-DAP v1 mode +DEBUG probe_rs::probe::stlink: Opening ST-Link: DebugProbeSelector { vendor_id: 4966, product_id: 4128, interface: None, serial_number: Some("000852004071") } +DEBUG probe_rs::probe::jlink: scanning 1 interfaces +DEBUG probe_rs::probe::jlink: J-Link interface is #0 +DEBUG probe_rs::probe::jlink: legacy caps: 3120528318 +DEBUG probe_rs::probe::jlink::capabilities: unknown capability bits: 0x28edcf16fb17c1db9ff7bbf truncated to 0x1b9ff7bbf +DEBUG probe_rs::probe::jlink: extended caps: 7415495614 +DEBUG probe_rs::probe::jlink: J-Link returned interface Fine, which is not supported by probe-rs. +DEBUG probe_rs::probe::jlink: J-Link returned interface Pic32Icsp, which is not supported by probe-rs. +DEBUG probe_rs::probe::jlink: J-Link returned interface Spi, which is not supported by probe-rs. +DEBUG probe_rs::probe::jlink: J-Link returned interface C2, which is not supported by probe-rs. +DEBUG probe_rs::probe::jlink: J-Link returned interface CJtag, which is not supported by probe-rs. +DEBUG probe_rs::probe::jlink: J-Link returned interface Mc2WireJtag, which is not supported by probe-rs. +DEBUG probe_rs::probe::jlink: J-Link max mem block size for SWD IO: 23704 byte +DEBUG probe_rs::probe::jlink: J-Link config: JlinkConfig { usb_address: Some(0), kickstart_power: None, ip_address: None, subnet_mask: None, mac_address: None } +DEBUG probe_rs::probe::jlink: Supported speeds: SpeedInfo { base_freq: 180000000, min_div: 12 } + INFO probe_rs::probe::jlink::speed: Selecting speed: 4000 Hz + INFO probe_rs::util::common_options: Protocol speed 4000 kHz +DEBUG probe_rs::probe::jlink: Attaching to J-Link +DEBUG probe_rs::probe::jlink: Attaching with protocol 'SWD' + INFO probe_rs::probe::jlink::speed: Selecting speed: 4000 Hz +DEBUG probe_rs::probe::jlink: J-Link: Capabilities: 7415495614 + INFO probe_rs::probe::jlink: J-Link: Firmware version: J-Link V12 compiled Mar 26 2026 10:14:53 + INFO probe_rs::probe::jlink: J-Link: Hardware version: J-Link 12.0.0 + INFO probe_rs::probe::jlink: J-Link: Target voltage: 3.28 V +DEBUG probe_rs::probe::jlink: Attached succesfully +DEBUG probe_rs::architecture::arm::communication_interface: Selecting DP Default +DEBUG probe_rs::architecture::arm::sequences: Setting up debug port Default +DEBUG probe_rs::architecture::arm::sequences: Performing SWD line reset +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: SWD: Connecting to debug port with address Default +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Performing SWD line reset +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Reading DPIDR to enable SWD interface +DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: DPIDR became readable after 0ms +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Result of DPIDR read: 0x2ba01477 +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Clearing errors using ABORT register +DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) +DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) +DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Result of CTRL/STAT read: Ctrl { .0: 4026535745, csyspwrupack: true, csyspwrupreq: true, cdbgpwrupack: true, cdbgpwrupreq: true, cdbgrstack: false, c_dbg_rst_req: false, errmode: false, trn_cnt: 0, mask_lane: 15, w_data_err: false, read_ok: true, sticky_err: false, stick_cmp: false, trn_mode: 0, sticky_orun: false, orun_detect: true } +DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Reading DP register DPIDR dp=Default +DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default +DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Read DP register DPIDR, value=0xDPIDR { .0: 2ba01477, revision: 00000002, part_no: 000000ba, min: false , version: 00000001, designer: 0000023b, jep_cc: 00000004, jep_id: 0000003b } dp=Default +DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Reading DP register CTRL/STAT dp=Default +DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default +DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Read DP register CTRL/STAT, value=0xCtrl { .0: f0000f41, csyspwrupack: true , csyspwrupreq: true , cdbgpwrupack: true , cdbgpwrupreq: true , cdbgrstack: false , c_dbg_rst_req: false , errmode: false , trn_cnt: 00000000, mask_lane: 0000000f, w_data_err: false , read_ok: true , sticky_err: false , stick_cmp: false , trn_mode: 00000000, sticky_orun: false , orun_detect: true } dp=Default +DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register ABORT, value=0x0000001f dp=Default register=Abort { .0: 31 } +DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default register=Abort { .0: 31 } +DEBUG read_dp_register: probe_rs::architecture::arm::dp: Reading DP register CTRL/STAT dp=Default +DEBUG read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default +DEBUG read_dp_register: probe_rs::architecture::arm::dp: Read DP register CTRL/STAT, value=0xCtrl { .0: f0000f41, csyspwrupack: true , csyspwrupreq: true , cdbgpwrupack: true , cdbgpwrupreq: true , cdbgrstack: false , c_dbg_rst_req: false , errmode: false , trn_cnt: 00000000, mask_lane: 0000000f, w_data_err: false , read_ok: true , sticky_err: false , stick_cmp: false , trn_mode: 00000000, sticky_orun: false , orun_detect: true } dp=Default +DEBUG read_dp_register: probe_rs::architecture::arm::dp: Reading DP register DPIDR dp=Default +DEBUG read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default +DEBUG read_dp_register: probe_rs::architecture::arm::dp: Read DP register DPIDR, value=0xDPIDR { .0: 2ba01477, revision: 00000002, part_no: 000000ba, min: false , version: 00000001, designer: 0000023b, jep_cc: 00000004, jep_id: 0000003b } dp=Default + INFO probe_rs::architecture::arm::communication_interface: Debug Port version: DPv1 MinDP: NotImplemented +DEBUG debug_device_unlock: probe_rs::architecture::arm::sequences: debug_device_unlock - empty by default +DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) id=0 +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) id=0 +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) id=0 +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) id=0 +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 ap=0 register="DRW" +DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful id=0 ap=0 register="DRW" value=16842752 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f0003 } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edfc id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 ap=0 register="DRW" +DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful id=0 ap=0 register="DRW" value=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edfc id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edfc id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000000 } id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 +DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block id=0 +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16973827 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=1 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::core::armv7m: Core was halted when connecting, reason: Request +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ef40 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ef40 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=269549601 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) + INFO probe_rs::session: Core 0 already halted + INFO probe_rs::session: Clearing breakpoints for core 0 +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002008 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002008 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000200c +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000200c } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002010 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002010 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002014 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002014 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002018 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002018 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000201c +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000201c } +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block + INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c0000, virtual address: 0x000c0000, flags: 0x4 + INFO probe_rs::flashing::download: Matching section: ".vector_table" + INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c02f0, virtual address: 0x000c02f0, flags: 0x5 + INFO probe_rs::flashing::download: Matching section: ".text" + INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c3944, virtual address: 0x000c3944, flags: 0x4 + INFO probe_rs::flashing::download: Matching section: ".rodata" + INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c4f80, virtual address: 0x00126d88, flags: 0x6 + INFO probe_rs::flashing::download: Matching section: ".data" + INFO probe_rs::flashing::loader: Found 4 loadable sections: + INFO probe_rs::flashing::loader: .vector_table at 0x000C0000 (752 bytes) + INFO probe_rs::flashing::loader: .text at 0x000C02F0 (13908 bytes) + INFO probe_rs::flashing::loader: .rodata at 0x000C3944 (5688 bytes) + INFO probe_rs::flashing::loader: .data at 0x000C4F80 (104 bytes) + Finished in 1.56s + INFO probe_rs::architecture::arm::sequences: Performing RAM flash start +DEBUG probe_rs::architecture::arm::sequences: RAM flash start for Cortex-M single core target +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x0c0000 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: c0000 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf8 +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf8 +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf8 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 126d88 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf4 +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf4 +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf4 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000d } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf8 +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf8 +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf8 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: c02f1 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf4 +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf4 +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf4 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000f } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 +DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed08 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed08 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed08 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: c0000 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault ap=0 register="DRW" +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=HardFault ap=0 register="DRW" value=196611 +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 30003 } condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edfc condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault ap=0 register="DRW" +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=HardFault ap=0 register="DRW" value=16777216 +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edfc condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edfc condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000400 } condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=HardFault +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset ap=0 register="DRW" +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=CoreReset ap=0 register="DRW" value=196611 +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 30003 } condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edfc condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset ap=0 register="DRW" +DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=CoreReset ap=0 register="DRW" value=16778240 +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edfc condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edfc condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000401 } condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset +DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=CoreReset +DEBUG probe_rs::rtt: Scanning at exact address: 0x00126d90 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block not found +DEBUG probe_rs::util::rtt::client: Clearing RTT control block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f000b } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f000d } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16973839 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=1 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG run: probe_rs::architecture::arm::core::armv7m: Reason for halt has changed, old reason was Halted(Request), new reason is Request +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196623 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG run: probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf4 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf4 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf4 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: f } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196623 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf8 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf8 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=795524 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196623 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f0007 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f0001 } +DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::rtt: Scanning at exact address: 0x00126d90 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } +DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) +DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" +DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 +DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words +DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) +DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block +DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) diff --git a/platform/dev-mec1723/mec1723_custom.yaml b/platform/dev-mec1723/mec1723_custom.yaml new file mode 100644 index 0000000..f831577 --- /dev/null +++ b/platform/dev-mec1723/mec1723_custom.yaml @@ -0,0 +1,46 @@ +name: Microchip MEC17xx Series Custom +generated_from_pack: true +pack_file_release: 1.4.221 +variants: +- name: MEC1723N_B0_SZ_CUSTOM + cores: + - name: main + type: armv7em + core_access_options: !Arm + ap: !v1 0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0xc0000 + end: 0x118000 + cores: + - main + - !Ram + name: IRAM2 + range: + start: 0x118000 + end: 0x128000 + cores: + - main + - !Generic + name: IRAM3 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + - !Generic + name: IRAM4 + range: + start: 0x40100000 + end: 0x40106000 + cores: + - main + - !Nvm + name: EXTFLASH + range: + start: 0x50000000 + end: 0x58000000 + cores: + - main diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs index 01b5715..7ff414c 100644 --- a/platform/dev-mec1723/src/board.rs +++ b/platform/dev-mec1723/src/board.rs @@ -7,7 +7,6 @@ bind_interrupts!(struct Irqs { /// Board IO for the dev-mec1723 platform. -#[allow(dead_code)] pub struct Board { pub uart: uart::Uart<'static, uart::Async>, } diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs index b2698ba..4e9cf1a 100644 --- a/platform/dev-mec1723/src/main.rs +++ b/platform/dev-mec1723/src/main.rs @@ -3,13 +3,13 @@ mod board; -//use board::Board; +use board::Board; use defmt::info; use defmt_rtt as _; use embassy_executor::Spawner; use embassy_microchip::uart; use panic_probe as _; -//use platform_common::board::BoardIo; +use platform_common::board::BoardIo; use platform_common::mock::MockOdpRelayHandler; use static_cell::StaticCell; @@ -24,33 +24,14 @@ async fn uart_service(uart: uart::Uart<'static, uart::Async>, relay: MockOdpRela panic!("uart-service error: {:?}", e); } -// #[embassy_executor::main] -// async fn main(spawner: Spawner) { -// info!("Booting..."); -// let p = embassy_microchip::init(embassy_microchip::config::Config::default()); -// let board = Board::init(p); - -// info!("Hello world from MEC1723!"); - -// let relay = platform_common::mock::init(spawner).await; -// spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); -// } - -use embassy_microchip::gpio::{Level, Output}; - #[embassy_executor::main] -async fn main(_spawner: Spawner) { - defmt::info!("RTT initialized!"); - +async fn main(spawner: Spawner) { + info!("Booting..."); let p = embassy_microchip::init(embassy_microchip::config::Config::default()); - - // Replace with actual LED GPIO from your board schematic - let mut led = Output::new(p.GPIO153, Level::Low); // example pin - - loop { - led.set_high(); - cortex_m::asm::delay(10_000_000); - led.set_low(); - cortex_m::asm::delay(10_000_000); - } + let board = Board::init(p); + + info!("Hello world from MEC1723!"); + + let relay = platform_common::mock::init(spawner).await; + spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); } \ No newline at end of file From 56c0bd47b45365cb22be319f9b9154a0fe3587c2 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Thu, 21 May 2026 18:42:52 -0700 Subject: [PATCH 08/15] no more uart error --- platform/dev-mec1723/Cargo.lock | 2 ++ platform/dev-mec1723/Cargo.toml | 2 ++ platform/dev-mec1723/Embed.toml | 16 ---------------- platform/dev-mec1723/src/board.rs | 8 ++++---- 4 files changed, 8 insertions(+), 20 deletions(-) delete mode 100644 platform/dev-mec1723/Embed.toml diff --git a/platform/dev-mec1723/Cargo.lock b/platform/dev-mec1723/Cargo.lock index 72e55d9..e991d46 100644 --- a/platform/dev-mec1723/Cargo.lock +++ b/platform/dev-mec1723/Cargo.lock @@ -303,6 +303,8 @@ dependencies = [ "defmt-rtt", "embassy-executor", "embassy-microchip", + "embassy-time", + "embedded-hal 0.2.7", "panic-probe", "platform-common", "static_cell", diff --git a/platform/dev-mec1723/Cargo.toml b/platform/dev-mec1723/Cargo.toml index dc214ea..f00c405 100644 --- a/platform/dev-mec1723/Cargo.toml +++ b/platform/dev-mec1723/Cargo.toml @@ -58,6 +58,8 @@ uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-servic "defmt", ] } static_cell = "2.1.0" +embassy-time = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embedded-hal = "0.2" platform-common = { path = "../platform-common", features = ["mock"] } panic-probe = { version = "1.0.0", features = ["print-defmt"] } diff --git a/platform/dev-mec1723/Embed.toml b/platform/dev-mec1723/Embed.toml deleted file mode 100644 index 2b1a6a6..0000000 --- a/platform/dev-mec1723/Embed.toml +++ /dev/null @@ -1,16 +0,0 @@ -[default.general] -chip = "MEC1723N_B0_SZ" - -[default.rtt] -enabled = true -timeout = 5000 - -[default.probe] -protocol = "Swd" -speed = 4000 - -[default.flashing] -enabled = true - -[default.reset] -halt_afterwards = false \ No newline at end of file diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs index 7ff414c..100142c 100644 --- a/platform/dev-mec1723/src/board.rs +++ b/platform/dev-mec1723/src/board.rs @@ -2,7 +2,7 @@ use platform_common::board::BoardIo; use embassy_microchip::{uart, bind_interrupts, peripherals, Peripherals}; bind_interrupts!(struct Irqs { - UART0 => uart::InterruptHandler::; + UART1 => uart::InterruptHandler::; }); @@ -18,9 +18,9 @@ impl BoardIo for Board { Board { /* Set up async UART on UART0 */ uart: uart::Uart::new_async( - p.UART0, - p.GPIO105, - p.GPIO104, + p.UART1, + p.GPIO171, + p.GPIO170, Irqs, uart::Config::default() ).expect("Failed to create 'uart' in 'Board'.") From 1f322122db86f1d55772dab67082c9983ef86df6 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Fri, 22 May 2026 14:10:06 -0700 Subject: [PATCH 09/15] buffered uart --- platform/dev-mec1723/Cargo.lock | 22 +++++++++++----------- platform/dev-mec1723/Cargo.toml | 20 ++++++++++---------- platform/dev-mec1723/src/board.rs | 3 +++ 3 files changed, 24 insertions(+), 21 deletions(-) diff --git a/platform/dev-mec1723/Cargo.lock b/platform/dev-mec1723/Cargo.lock index e991d46..50b0d51 100644 --- a/platform/dev-mec1723/Cargo.lock +++ b/platform/dev-mec1723/Cargo.lock @@ -333,7 +333,7 @@ dependencies = [ [[package]] name = "embassy-embedded-hal" version = "0.6.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "embassy-futures", "embassy-hal-internal", @@ -349,7 +349,7 @@ dependencies = [ [[package]] name = "embassy-executor" version = "0.10.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "cordyceps", "cortex-m", @@ -363,7 +363,7 @@ dependencies = [ [[package]] name = "embassy-executor-macros" version = "0.8.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "darling", "proc-macro2", @@ -374,17 +374,17 @@ dependencies = [ [[package]] name = "embassy-executor-timer-queue" version = "0.1.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" [[package]] name = "embassy-futures" version = "0.1.2" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" [[package]] name = "embassy-hal-internal" version = "0.5.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "cortex-m", "critical-section", @@ -395,7 +395,7 @@ dependencies = [ [[package]] name = "embassy-microchip" version = "0.1.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "cortex-m", "cortex-m-rt", @@ -423,7 +423,7 @@ dependencies = [ [[package]] name = "embassy-sync" version = "0.8.0" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "cfg-if", "critical-section", @@ -437,7 +437,7 @@ dependencies = [ [[package]] name = "embassy-time" version = "0.5.1" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "cfg-if", "critical-section", @@ -453,7 +453,7 @@ dependencies = [ [[package]] name = "embassy-time-driver" version = "0.2.2" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "document-features", ] @@ -461,7 +461,7 @@ dependencies = [ [[package]] name = "embassy-time-queue-utils" version = "0.3.2" -source = "git+https://github.com/embassy-rs/embassy?rev=bb3dbfb706288d9dbc907632340ac505561455c6#bb3dbfb706288d9dbc907632340ac505561455c6" +source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "embassy-executor-timer-queue", "heapless 0.9.3", diff --git a/platform/dev-mec1723/Cargo.toml b/platform/dev-mec1723/Cargo.toml index f00c405..0095bb2 100644 --- a/platform/dev-mec1723/Cargo.toml +++ b/platform/dev-mec1723/Cargo.toml @@ -49,7 +49,7 @@ embassy-executor = { version = "0.10.0", default-features = false, features = [ "executor-interrupt", "defmt", ] } -embassy-microchip = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6", features = [ +embassy-microchip = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788", features = [ "defmt", "mec1723n_b0_sz", # u_Note: the dev board i have with me says 'SZ' on it "rt", @@ -58,7 +58,7 @@ uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-servic "defmt", ] } static_cell = "2.1.0" -embassy-time = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } embedded-hal = "0.2" platform-common = { path = "../platform-common", features = ["mock"] } panic-probe = { version = "1.0.0", features = ["print-defmt"] } @@ -71,11 +71,11 @@ ignored = ["cortex-m", "cortex-m-rt"] # embassy-time/embassy-time-driver from crates.io, which would cause a duplicate # `links` conflict. Force everyone to use the git versions. [patch.crates-io] -embassy-time = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-time-driver = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-time-queue-utils = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-sync = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-executor = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-futures = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-embedded-hal = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } -embassy-hal-internal = { git = "https://github.com/embassy-rs/embassy", rev = "bb3dbfb706288d9dbc907632340ac505561455c6" } +embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-time-driver = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-time-queue-utils = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-sync = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-executor = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-futures = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-embedded-hal = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-hal-internal = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs index 100142c..653abb8 100644 --- a/platform/dev-mec1723/src/board.rs +++ b/platform/dev-mec1723/src/board.rs @@ -1,10 +1,12 @@ use platform_common::board::BoardIo; use embassy_microchip::{uart, bind_interrupts, peripherals, Peripherals}; +use static_cell::ConstStaticCell; bind_interrupts!(struct Irqs { UART1 => uart::InterruptHandler::; }); +static UART_BUFFER: ConstStaticCell<[u8; 1024]> = ConstStaticCell::new([0u8; 1024]); /// Board IO for the dev-mec1723 platform. pub struct Board { @@ -22,6 +24,7 @@ impl BoardIo for Board { p.GPIO171, p.GPIO170, Irqs, + UART_BUFFER.take(), uart::Config::default() ).expect("Failed to create 'uart' in 'Board'.") } From 7a0a9f557668151b2463379a0ee8b53d96bba81d Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Fri, 22 May 2026 15:21:19 -0700 Subject: [PATCH 10/15] rebase --- platform/dev-mec1723/Cargo.lock | 108 +++++++++++++++---------------- platform/dev-mec1723/src/main.rs | 4 +- 2 files changed, 55 insertions(+), 57 deletions(-) diff --git a/platform/dev-mec1723/Cargo.lock b/platform/dev-mec1723/Cargo.lock index 50b0d51..89075e8 100644 --- a/platform/dev-mec1723/Cargo.lock +++ b/platform/dev-mec1723/Cargo.lock @@ -13,9 +13,9 @@ dependencies = [ [[package]] name = "autocfg" -version = "1.5.0" +version = "1.5.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" +checksum = "f2032f911046de80f0a198e0901378627c33f59ea0ac00e363d481118bd70a53" [[package]] name = "az" @@ -35,7 +35,7 @@ dependencies = [ [[package]] name = "battery-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "battery-service-interface", "defmt 0.3.100", @@ -51,7 +51,7 @@ dependencies = [ [[package]] name = "battery-service-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embedded-batteries-async", @@ -60,7 +60,7 @@ dependencies = [ [[package]] name = "battery-service-relay" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "battery-service-interface", "defmt 0.3.100", @@ -68,6 +68,14 @@ dependencies = [ "num_enum", ] +[[package]] +name = "bit-register" +version = "0.1.0" +source = "git+https://github.com/OpenDevicePartnership/odp-utilities?tag=v0.1.0#583015c08ad9855f310bdb25d5cf9abff77b5e08" +dependencies = [ + "num-traits", +] + [[package]] name = "bit-register" version = "0.1.0" @@ -138,9 +146,9 @@ checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" [[package]] name = "cc" -version = "1.2.61" +version = "1.2.62" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d16d90359e986641506914ba71350897565610e87ce0ad9e6f28569db3dd5c6d" +checksum = "a1dce859f0832a7d088c4f1119888ab94ef4b5d6795d1ce05afb7fe159d79f98" dependencies = [ "find-msvc-tools", "shlex", @@ -248,14 +256,14 @@ version = "0.3.100" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f0963443817029b2024136fc4dd07a5107eb8f977eaf18fcd1fdeb11306b64ad" dependencies = [ - "defmt 1.0.1", + "defmt 1.1.0", ] [[package]] name = "defmt" -version = "1.0.1" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "548d977b6da32fa1d1fda2876453da1e7df63ad0304c8b3dae4dbe7b96f39b78" +checksum = "a6e524506490a1953d237cb87b1cfc1e46f88c18f10a22dfe0f507dc6bfc7f7f" dependencies = [ "bitflags 1.3.2", "defmt-macros", @@ -263,9 +271,9 @@ dependencies = [ [[package]] name = "defmt-macros" -version = "1.0.1" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3d4fc12a85bcf441cfe44344c4b72d58493178ce635338a3f3b78943aceb258e" +checksum = "f0a27770e9c8f719a79d8b638281f4d828f77d8fd61e0bd94451b9b85e576a0b" dependencies = [ "defmt-parser", "proc-macro-error2", @@ -285,12 +293,12 @@ dependencies = [ [[package]] name = "defmt-rtt" -version = "1.1.0" +version = "1.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "93d5a25c99d89c40f5676bec8cefe0614f17f0f40e916f98e345dae941807f9e" +checksum = "c0f73a4a4a91609e977ae3b7bd831ffa292edfd42ad140a3244a61d805b0e05e" dependencies = [ "critical-section", - "defmt 1.0.1", + "defmt 1.1.0", ] [[package]] @@ -299,7 +307,7 @@ version = "0.1.0" dependencies = [ "cortex-m", "cortex-m-rt", - "defmt 1.0.1", + "defmt 1.1.0", "defmt-rtt", "embassy-executor", "embassy-microchip", @@ -354,7 +362,7 @@ dependencies = [ "cordyceps", "cortex-m", "critical-section", - "defmt 1.0.1", + "defmt 1.1.0", "document-features", "embassy-executor-macros", "embassy-executor-timer-queue", @@ -388,7 +396,7 @@ source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74c dependencies = [ "cortex-m", "critical-section", - "defmt 1.0.1", + "defmt 1.1.0", "num-traits", ] @@ -400,7 +408,7 @@ dependencies = [ "cortex-m", "cortex-m-rt", "critical-section", - "defmt 1.0.1", + "defmt 1.1.0", "document-features", "embassy-embedded-hal", "embassy-futures", @@ -427,11 +435,11 @@ source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74c dependencies = [ "cfg-if", "critical-section", - "defmt 1.0.1", + "defmt 1.1.0", "embedded-io-async 0.7.0", "futures-core", "futures-sink", - "heapless 0.9.3", + "heapless", ] [[package]] @@ -441,7 +449,7 @@ source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74c dependencies = [ "cfg-if", "critical-section", - "defmt 1.0.1", + "defmt 1.1.0", "document-features", "embassy-time-driver", "embedded-hal 0.2.7", @@ -464,7 +472,7 @@ version = "0.3.2" source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" dependencies = [ "embassy-executor-timer-queue", - "heapless 0.9.3", + "heapless", ] [[package]] @@ -504,7 +512,7 @@ version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "0e5007eb97aabfe3606c0b02823b3120e861c748ed3560756aa4fd231ef9ebf0" dependencies = [ - "defmt 1.0.1", + "defmt 1.1.0", ] [[package]] @@ -513,7 +521,7 @@ version = "0.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "bafd19dc3b6aaa5027856818e19ccbfe84ebfb094c8a0ecf84a20e75c3b8e959" dependencies = [ - "defmt 1.0.1", + "defmt 1.1.0", "embedded-fans", ] @@ -588,7 +596,7 @@ version = "0.2.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f02b992c2b871b7fc616e4539258d92ea8b085e2f09cc0ad2862aa4d0e185ad1" dependencies = [ - "defmt 1.0.1", + "defmt 1.1.0", "num_enum", ] @@ -598,7 +606,7 @@ version = "0.1.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "8c703756bee31e7aaf55d8fb6dcf7337cfc231cfb4a3ad34b9df509846fd9001" dependencies = [ - "defmt 1.0.1", + "defmt 1.1.0", "paste", ] @@ -608,7 +616,7 @@ version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "51c524a78b2804eca0d9ec05154e51d9af948b40cd0a6bbcc4d5832ff7e47b5b" dependencies = [ - "defmt 1.0.1", + "defmt 1.1.0", "embedded-sensors-hal", "paste", ] @@ -616,7 +624,7 @@ dependencies = [ [[package]] name = "embedded-services" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "bitfield 0.17.0", "cortex-m", @@ -648,9 +656,9 @@ dependencies = [ [[package]] name = "espi-device" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/haf-ec-service#09eda26a729738adbd177231600acdb981690375" +source = "git+https://github.com/OpenDevicePartnership/haf-ec-service#290aa80a4c281857f3bed94581200b330119286c" dependencies = [ - "bit-register", + "bit-register 0.1.0 (git+https://github.com/OpenDevicePartnership/odp-utilities?tag=v0.1.0)", "bitflags 2.11.1", "num-traits", "num_enum", @@ -729,16 +737,6 @@ dependencies = [ "byteorder", ] -[[package]] -name = "heapless" -version = "0.8.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0bfb9eb618601c89945a70e254898da93b13be0388091d42117462b265bb3fad" -dependencies = [ - "hash32", - "stable_deref_trait", -] - [[package]] name = "heapless" version = "0.9.3" @@ -810,9 +808,9 @@ dependencies = [ [[package]] name = "mctp-rs" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ - "bit-register", + "bit-register 0.1.0 (git+https://github.com/OpenDevicePartnership/odp-utilities)", "defmt 0.3.100", "embedded-batteries", "espi-device", @@ -829,7 +827,7 @@ checksum = "5f21dce65d8af922b93d08336f6450629f51d1d1c7561ffe01b7cac4e735192d" dependencies = [ "cortex-m", "cortex-m-rt", - "defmt 1.0.1", + "defmt 1.1.0", ] [[package]] @@ -895,7 +893,7 @@ dependencies = [ [[package]] name = "odp-service-common" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "embedded-services", "static_cell", @@ -914,7 +912,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "fd402d00b0fb94c5aee000029204a46884b1262e0c443f166d86d2c0747e1a1a" dependencies = [ "cortex-m", - "defmt 1.0.1", + "defmt 1.1.0", ] [[package]] @@ -970,7 +968,7 @@ checksum = "c33a9471896f1c69cecef8d20cbe2f7accd12527ce60845ff44c153bb2a21b49" [[package]] name = "power-policy-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "bitfield 0.17.0", "defmt 0.3.100", @@ -1186,7 +1184,7 @@ dependencies = [ [[package]] name = "thermal-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embassy-futures", @@ -1195,7 +1193,7 @@ dependencies = [ "embedded-fans-async", "embedded-sensors-hal-async", "embedded-services", - "heapless 0.8.0", + "heapless", "odp-service-common", "thermal-service-interface", ] @@ -1203,7 +1201,7 @@ dependencies = [ [[package]] name = "thermal-service-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embassy-time", @@ -1214,7 +1212,7 @@ dependencies = [ [[package]] name = "thermal-service-relay" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embedded-services", @@ -1255,7 +1253,7 @@ dependencies = [ [[package]] name = "time-alarm-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embassy-futures", @@ -1271,7 +1269,7 @@ dependencies = [ [[package]] name = "time-alarm-service-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "bitfield 0.17.0", "defmt 0.3.100", @@ -1283,7 +1281,7 @@ dependencies = [ [[package]] name = "time-alarm-service-relay" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embedded-mcu-hal", @@ -1362,7 +1360,7 @@ checksum = "40ce102ab67701b8526c123c1bab5cbe42d7040ccfd0f64af1a385808d2f43de" [[package]] name = "uart-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#bd46037d63c0b39ccd73a23fffeb328dea8fea00" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" dependencies = [ "defmt 0.3.100", "embassy-sync", diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs index 4e9cf1a..f4296e3 100644 --- a/platform/dev-mec1723/src/main.rs +++ b/platform/dev-mec1723/src/main.rs @@ -16,8 +16,8 @@ use static_cell::StaticCell; #[embassy_executor::task] async fn uart_service(uart: uart::Uart<'static, uart::Async>, relay: MockOdpRelayHandler) { info!("Starting uart service"); - static UART_SERVICE: StaticCell> = StaticCell::new(); - let uart_service = uart_service::Service::new(relay).unwrap(); + static UART_SERVICE: StaticCell> = StaticCell::new(); + let uart_service = uart_service::DefaultService::default_smbusespi(relay).unwrap(); let uart_service = UART_SERVICE.init(uart_service); let Err(e) = uart_service::task::uart_service(uart_service, uart).await; From cb50d3479b11d43ffefe7d71418f888a102c7aa0 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Sat, 23 May 2026 13:29:42 -0700 Subject: [PATCH 11/15] update embassy-microchip fork and turn off [TRACE] logs --- platform/dev-mec1723/.cargo/config.toml | 2 +- platform/dev-mec1723/.gitignore | 2 + platform/dev-mec1723/Cargo.lock | 22 +- platform/dev-mec1723/Cargo.toml | 20 +- platform/dev-mec1723/debug.log | 1127 ----------------------- 5 files changed, 24 insertions(+), 1149 deletions(-) create mode 100644 platform/dev-mec1723/.gitignore delete mode 100644 platform/dev-mec1723/debug.log diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml index 79fd310..0b5de89 100644 --- a/platform/dev-mec1723/.cargo/config.toml +++ b/platform/dev-mec1723/.cargo/config.toml @@ -18,4 +18,4 @@ rustflags = [ target = "thumbv7em-none-eabihf" [env] -DEFMT_LOG = "trace" +DEFMT_LOG = "info" diff --git a/platform/dev-mec1723/.gitignore b/platform/dev-mec1723/.gitignore new file mode 100644 index 0000000..48aa3df --- /dev/null +++ b/platform/dev-mec1723/.gitignore @@ -0,0 +1,2 @@ +target/ +*.log \ No newline at end of file diff --git a/platform/dev-mec1723/Cargo.lock b/platform/dev-mec1723/Cargo.lock index 89075e8..1257a14 100644 --- a/platform/dev-mec1723/Cargo.lock +++ b/platform/dev-mec1723/Cargo.lock @@ -341,7 +341,7 @@ dependencies = [ [[package]] name = "embassy-embedded-hal" version = "0.6.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "embassy-futures", "embassy-hal-internal", @@ -357,7 +357,7 @@ dependencies = [ [[package]] name = "embassy-executor" version = "0.10.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "cordyceps", "cortex-m", @@ -371,7 +371,7 @@ dependencies = [ [[package]] name = "embassy-executor-macros" version = "0.8.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "darling", "proc-macro2", @@ -382,17 +382,17 @@ dependencies = [ [[package]] name = "embassy-executor-timer-queue" version = "0.1.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" [[package]] name = "embassy-futures" version = "0.1.2" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" [[package]] name = "embassy-hal-internal" version = "0.5.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "cortex-m", "critical-section", @@ -403,7 +403,7 @@ dependencies = [ [[package]] name = "embassy-microchip" version = "0.1.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "cortex-m", "cortex-m-rt", @@ -431,7 +431,7 @@ dependencies = [ [[package]] name = "embassy-sync" version = "0.8.0" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "cfg-if", "critical-section", @@ -445,7 +445,7 @@ dependencies = [ [[package]] name = "embassy-time" version = "0.5.1" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "cfg-if", "critical-section", @@ -461,7 +461,7 @@ dependencies = [ [[package]] name = "embassy-time-driver" version = "0.2.2" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "document-features", ] @@ -469,7 +469,7 @@ dependencies = [ [[package]] name = "embassy-time-queue-utils" version = "0.3.2" -source = "git+https://github.com/bjackson312006/embassy?rev=16a061f3610bafcee74cc5e4feb350c72e1c5788#16a061f3610bafcee74cc5e4feb350c72e1c5788" +source = "git+https://github.com/bjackson312006/embassy?rev=e85b387cf915241a1d9e0ba32ab4a7a1117896b3#e85b387cf915241a1d9e0ba32ab4a7a1117896b3" dependencies = [ "embassy-executor-timer-queue", "heapless", diff --git a/platform/dev-mec1723/Cargo.toml b/platform/dev-mec1723/Cargo.toml index 0095bb2..67aeb79 100644 --- a/platform/dev-mec1723/Cargo.toml +++ b/platform/dev-mec1723/Cargo.toml @@ -49,7 +49,7 @@ embassy-executor = { version = "0.10.0", default-features = false, features = [ "executor-interrupt", "defmt", ] } -embassy-microchip = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788", features = [ +embassy-microchip = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3", features = [ "defmt", "mec1723n_b0_sz", # u_Note: the dev board i have with me says 'SZ' on it "rt", @@ -58,7 +58,7 @@ uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-servic "defmt", ] } static_cell = "2.1.0" -embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } embedded-hal = "0.2" platform-common = { path = "../platform-common", features = ["mock"] } panic-probe = { version = "1.0.0", features = ["print-defmt"] } @@ -71,11 +71,11 @@ ignored = ["cortex-m", "cortex-m-rt"] # embassy-time/embassy-time-driver from crates.io, which would cause a duplicate # `links` conflict. Force everyone to use the git versions. [patch.crates-io] -embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-time-driver = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-time-queue-utils = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-sync = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-executor = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-futures = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-embedded-hal = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } -embassy-hal-internal = { git = "https://github.com/bjackson312006/embassy", rev = "16a061f3610bafcee74cc5e4feb350c72e1c5788" } +embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-time-driver = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-time-queue-utils = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-sync = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-executor = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-futures = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-embedded-hal = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } +embassy-hal-internal = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } diff --git a/platform/dev-mec1723/debug.log b/platform/dev-mec1723/debug.log deleted file mode 100644 index 2dada00..0000000 --- a/platform/dev-mec1723/debug.log +++ /dev/null @@ -1,1127 +0,0 @@ - Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.08s - Running `probe-rs run --chip MEC1723N_B0_SZ --protocol swd --speed 4000 target/thumbv7em-none-eabihf/debug/dev-mec1723` -DEBUG probe_rs::cmd::run: No .embedded_test linker section in ELF -DEBUG probe_rs::cmd::run: No embedded-test in ELF file. Running as normal -DEBUG list_cmsisdap_devices: probe_rs::probe::cmsisdap::tools: Searching for CMSIS-DAP probes using nusb -DEBUG list_cmsisdap_devices: probe_rs::probe::cmsisdap::tools: Found 0 CMSIS-DAP probes using nusb, searching HID -DEBUG list_cmsisdap_devices: probe_rs::probe::cmsisdap::tools: Found 0 CMSIS-DAP probes total -DEBUG list_wlink_devices: probe_rs::probe::wlink: Searching for WCH-Link(RV) probes -DEBUG list_wlink_devices: probe_rs::probe::wlink: Found 0 WCH-Link probes total -DEBUG probe_rs::config::registry: Searching registry for chip with name MEC1723N_B0_SZ -DEBUG probe_rs::config::registry: Exact match for chip name: MEC1723N_B0_SZ - INFO probe_rs::config::target: Using sequence Arm(Mec172x) -DEBUG probe_rs::probe::cmsisdap::tools: Attempting to open 1366:1020 in CMSIS-DAP v1 mode -DEBUG probe_rs::probe::stlink: Opening ST-Link: DebugProbeSelector { vendor_id: 4966, product_id: 4128, interface: None, serial_number: Some("000852004071") } -DEBUG probe_rs::probe::jlink: scanning 1 interfaces -DEBUG probe_rs::probe::jlink: J-Link interface is #0 -DEBUG probe_rs::probe::jlink: legacy caps: 3120528318 -DEBUG probe_rs::probe::jlink::capabilities: unknown capability bits: 0x28edcf16fb17c1db9ff7bbf truncated to 0x1b9ff7bbf -DEBUG probe_rs::probe::jlink: extended caps: 7415495614 -DEBUG probe_rs::probe::jlink: J-Link returned interface Fine, which is not supported by probe-rs. -DEBUG probe_rs::probe::jlink: J-Link returned interface Pic32Icsp, which is not supported by probe-rs. -DEBUG probe_rs::probe::jlink: J-Link returned interface Spi, which is not supported by probe-rs. -DEBUG probe_rs::probe::jlink: J-Link returned interface C2, which is not supported by probe-rs. -DEBUG probe_rs::probe::jlink: J-Link returned interface CJtag, which is not supported by probe-rs. -DEBUG probe_rs::probe::jlink: J-Link returned interface Mc2WireJtag, which is not supported by probe-rs. -DEBUG probe_rs::probe::jlink: J-Link max mem block size for SWD IO: 23704 byte -DEBUG probe_rs::probe::jlink: J-Link config: JlinkConfig { usb_address: Some(0), kickstart_power: None, ip_address: None, subnet_mask: None, mac_address: None } -DEBUG probe_rs::probe::jlink: Supported speeds: SpeedInfo { base_freq: 180000000, min_div: 12 } - INFO probe_rs::probe::jlink::speed: Selecting speed: 4000 Hz - INFO probe_rs::util::common_options: Protocol speed 4000 kHz -DEBUG probe_rs::probe::jlink: Attaching to J-Link -DEBUG probe_rs::probe::jlink: Attaching with protocol 'SWD' - INFO probe_rs::probe::jlink::speed: Selecting speed: 4000 Hz -DEBUG probe_rs::probe::jlink: J-Link: Capabilities: 7415495614 - INFO probe_rs::probe::jlink: J-Link: Firmware version: J-Link V12 compiled Mar 26 2026 10:14:53 - INFO probe_rs::probe::jlink: J-Link: Hardware version: J-Link 12.0.0 - INFO probe_rs::probe::jlink: J-Link: Target voltage: 3.28 V -DEBUG probe_rs::probe::jlink: Attached succesfully -DEBUG probe_rs::architecture::arm::communication_interface: Selecting DP Default -DEBUG probe_rs::architecture::arm::sequences: Setting up debug port Default -DEBUG probe_rs::architecture::arm::sequences: Performing SWD line reset -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: SWD: Connecting to debug port with address Default -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Performing SWD line reset -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Reading DPIDR to enable SWD interface -DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: DPIDR became readable after 0ms -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Result of DPIDR read: 0x2ba01477 -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Clearing errors using ABORT register -DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) -DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG debug_port_connect: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) -DEBUG debug_port_connect: probe_rs::architecture::arm::sequences: Result of CTRL/STAT read: Ctrl { .0: 4026535745, csyspwrupack: true, csyspwrupreq: true, cdbgpwrupack: true, cdbgpwrupreq: true, cdbgrstack: false, c_dbg_rst_req: false, errmode: false, trn_cnt: 0, mask_lane: 15, w_data_err: false, read_ok: true, sticky_err: false, stick_cmp: false, trn_mode: 0, sticky_orun: false, orun_detect: true } -DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Reading DP register DPIDR dp=Default -DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default -DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Read DP register DPIDR, value=0xDPIDR { .0: 2ba01477, revision: 00000002, part_no: 000000ba, min: false , version: 00000001, designer: 0000023b, jep_cc: 00000004, jep_id: 0000003b } dp=Default -DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Reading DP register CTRL/STAT dp=Default -DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default -DEBUG debug_port_start:read_dp_register: probe_rs::architecture::arm::dp: Read DP register CTRL/STAT, value=0xCtrl { .0: f0000f41, csyspwrupack: true , csyspwrupreq: true , cdbgpwrupack: true , cdbgpwrupreq: true , cdbgrstack: false , c_dbg_rst_req: false , errmode: false , trn_cnt: 00000000, mask_lane: 0000000f, w_data_err: false , read_ok: true , sticky_err: false , stick_cmp: false , trn_mode: 00000000, sticky_orun: false , orun_detect: true } dp=Default -DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register ABORT, value=0x0000001f dp=Default register=Abort { .0: 31 } -DEBUG debug_port_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default register=Abort { .0: 31 } -DEBUG read_dp_register: probe_rs::architecture::arm::dp: Reading DP register CTRL/STAT dp=Default -DEBUG read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default -DEBUG read_dp_register: probe_rs::architecture::arm::dp: Read DP register CTRL/STAT, value=0xCtrl { .0: f0000f41, csyspwrupack: true , csyspwrupreq: true , cdbgpwrupack: true , cdbgpwrupreq: true , cdbgrstack: false , c_dbg_rst_req: false , errmode: false , trn_cnt: 00000000, mask_lane: 0000000f, w_data_err: false , read_ok: true , sticky_err: false , stick_cmp: false , trn_mode: 00000000, sticky_orun: false , orun_detect: true } dp=Default -DEBUG read_dp_register: probe_rs::architecture::arm::dp: Reading DP register DPIDR dp=Default -DEBUG read_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 1 transfers (0 additional transfers) dp=Default -DEBUG read_dp_register: probe_rs::architecture::arm::dp: Read DP register DPIDR, value=0xDPIDR { .0: 2ba01477, revision: 00000002, part_no: 000000ba, min: false , version: 00000001, designer: 0000023b, jep_cc: 00000004, jep_id: 0000003b } dp=Default - INFO probe_rs::architecture::arm::communication_interface: Debug Port version: DPv1 MinDP: NotImplemented -DEBUG debug_device_unlock: probe_rs::architecture::arm::sequences: debug_device_unlock - empty by default -DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) id=0 -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) id=0 -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) id=0 -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) id=0 -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG debug_core_start:write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 ap=0 register="DRW" -DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful id=0 ap=0 register="DRW" value=16842752 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f0003 } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edfc id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 ap=0 register="DRW" -DEBUG debug_core_start:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful id=0 ap=0 register="DRW" value=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edfc id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edfc id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000000 } id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) id=0 -DEBUG debug_core_start: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block id=0 -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16973827 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=1 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::core::armv7m: Core was halted when connecting, reason: Request -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ef40 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ef40 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=269549601 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) - INFO probe_rs::session: Core 0 already halted - INFO probe_rs::session: Clearing breakpoints for core 0 -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002008 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002008 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000200c -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000200c } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002010 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002010 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002014 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002014 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002018 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002018 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe0002000 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e0002000 } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=608 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000201c -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000201c } -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG clear_all_hw_breakpoints:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG clear_all_hw_breakpoints: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block - INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c0000, virtual address: 0x000c0000, flags: 0x4 - INFO probe_rs::flashing::download: Matching section: ".vector_table" - INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c02f0, virtual address: 0x000c02f0, flags: 0x5 - INFO probe_rs::flashing::download: Matching section: ".text" - INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c3944, virtual address: 0x000c3944, flags: 0x4 - INFO probe_rs::flashing::download: Matching section: ".rodata" - INFO probe_rs::flashing::download: Found loadable segment, physical address: 0x000c4f80, virtual address: 0x00126d88, flags: 0x6 - INFO probe_rs::flashing::download: Matching section: ".data" - INFO probe_rs::flashing::loader: Found 4 loadable sections: - INFO probe_rs::flashing::loader: .vector_table at 0x000C0000 (752 bytes) - INFO probe_rs::flashing::loader: .text at 0x000C02F0 (13908 bytes) - INFO probe_rs::flashing::loader: .rodata at 0x000C3944 (5688 bytes) - INFO probe_rs::flashing::loader: .data at 0x000C4F80 (104 bytes) - Finished in 1.56s - INFO probe_rs::architecture::arm::sequences: Performing RAM flash start -DEBUG probe_rs::architecture::arm::sequences: RAM flash start for Cortex-M single core target -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x0c0000 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: c0000 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf8 -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf8 -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf8 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 126d88 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf4 -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf4 -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf4 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000d } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf8 -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf8 -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf8 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: c02f1 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf4 -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf4 -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf4 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000f } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG write_core_reg: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG write_core_reg: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG write_core_reg:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 -DEBUG write_core_reg: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed08 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed08 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed08 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: c0000 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault ap=0 register="DRW" -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=HardFault ap=0 register="DRW" value=196611 -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 30003 } condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edfc condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault ap=0 register="DRW" -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=HardFault ap=0 register="DRW" value=16777216 -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edfc condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edfc condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000400 } condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=HardFault -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset ap=0 register="DRW" -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=CoreReset ap=0 register="DRW" value=196611 -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 30003 } condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edfc condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset ap=0 register="DRW" -DEBUG enable_vector_catch:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful condition=CoreReset ap=0 register="DRW" value=16778240 -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edfc condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edfc condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edfc } condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1000401 } condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) condition=CoreReset -DEBUG enable_vector_catch: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block condition=CoreReset -DEBUG probe_rs::rtt: Scanning at exact address: 0x00126d90 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block not found -DEBUG probe_rs::util::rtt::client: Clearing RTT control block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196611 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f000b } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f000d } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16973839 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=1 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG run: probe_rs::architecture::arm::core::armv7m: Reason for halt has changed, old reason was Halted(Request), new reason is Request -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196623 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000ed30 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=0 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000ed30 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000ed30 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000ed30 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: 1f } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG run: probe_rs::architecture::arm::core::armv7m: Cached halt reason: Halted(Request) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf4 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf4 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf4 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: f } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196623 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf8 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf8 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=795524 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run:read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG run:read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=196623 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f0007 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Write block with total size 4 bytes to address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Writing chunk with len 1 at address 0xe000edf0 -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::ap: Writing AP register DRW, value=DRW { data: a05f0001 } -DEBUG run: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG run: probe_rs::architecture::arm::memory::adi_memory_interface: Finished writing block -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::rtt: Scanning at exact address: 0x00126d90 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap::memory_ap: reading IDR: IDR { REVISION: 2, DESIGNER: JEP106Code({ cc: 0x04, id: 0x3b } => Some("ARM Ltd")), CLASS: MemAp, _RES0: 0, VARIANT: 1, TYPE: AmbaAhb3 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: f0, ap_sel: 0, ap_bank_sel: f, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x000000f0 dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 240, ap_sel: 0, ap_bank_sel: 15, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Writing AP register CSW, value=CSW { DbgSwEnable: true, HNONSEC: true, MasterType: true, Allocate: false, Cacheable: true, Bufferable: false, Privileged: true, Data: true, SPIDEN: false, TrInProg: false, DeviceEn: true, AddrInc: Single, Size: U32, _reserved_bits: 0 } -DEBUG probe_rs::architecture::arm::communication_interface: Changing SELECT to DPv1(SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 }) -DEBUG write_dp_register: probe_rs::architecture::arm::dp: Writing DP register SELECT, value=0x00000000 dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG write_dp_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) dp=Default register=SelectV1 { .0: 0, ap_sel: 0, ap_bank_sel: 0, dp_bank_sel: 0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 1 at address 0xe000edf0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: e000edf0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG read_ap_register: probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) ap=0 register="DRW" -DEBUG read_ap_register: probe_rs::architecture::arm::ap: Register read succesful ap=0 register="DRW" value=16842753 -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 4 at address 0x126d90 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126d90 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=4 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 5 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126da0 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da0 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 6 at address 0x126da8 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126da8 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=6 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 7 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Reading chunk with len 2 at address 0x126db4 -DEBUG probe_rs::architecture::arm::ap: Writing AP register TAR, value=TAR { address: 126db4 } -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 2 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::ap: Reading register DRW, block with len=2 words -DEBUG probe_rs::architecture::arm::traits::polyfill: Performing 3 transfers (1 additional transfers) -DEBUG probe_rs::architecture::arm::memory::adi_memory_interface: Finished reading block -DEBUG probe_rs::util::rtt::client: Failed to attach - control block corrupted: the write buffer doesn't fully fit in any known (consecutive) ram region according to its own pointers: (start_pointer: 0x1273FC, size: 1024) From b712396dd54368badd5a50472f2e8c97c9187035 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Sat, 23 May 2026 13:57:15 -0700 Subject: [PATCH 12/15] removed custom yaml, adjusted memory.x and link_ram.x to be consistent with the embassy example --- platform/dev-mec1723/.cargo/config.toml | 22 +- platform/dev-mec1723/Cargo.toml | 2 +- .../dev-mec1723/dev-mec1723.code-workspace | 2 +- platform/dev-mec1723/link_ram.x | 280 ++++++++++++++++++ platform/dev-mec1723/mec1723_custom.yaml | 46 --- platform/dev-mec1723/memory.x | 11 +- 6 files changed, 292 insertions(+), 71 deletions(-) create mode 100644 platform/dev-mec1723/link_ram.x delete mode 100644 platform/dev-mec1723/mec1723_custom.yaml diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml index 0b5de89..f1cc30c 100644 --- a/platform/dev-mec1723/.cargo/config.toml +++ b/platform/dev-mec1723/.cargo/config.toml @@ -1,21 +1,17 @@ [target.thumbv7em-none-eabihf] -runner = 'probe-rs run --chip-description-path mec1723_custom.yaml --chip MEC1723N_B0_SZ_CUSTOM --protocol swd --speed 4000' +runner = 'probe-rs run --chip MEC1723N_B0_SZ' rustflags = [ - "-C", - "linker=flip-link", - "-C", - "link-arg=-Tlink.x", - "-C", - "link-arg=-Tdefmt.x", - # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x - # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 - "-C", - "link-arg=--nmagic", + # "-C", "linker=flip-link", + "-C", "link-arg=-Tlink_ram.x", + "-C", "link-arg=-Tdefmt.x", + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", ] [build] -target = "thumbv7em-none-eabihf" +target = "thumbv7em-none-eabihf" # Cortex-M4F [env] -DEFMT_LOG = "info" +DEFMT_LOG = "info" # Note: printing out too many defmt/RTT messages can interfere with UART reliability so probably adjust logging level accordingly \ No newline at end of file diff --git a/platform/dev-mec1723/Cargo.toml b/platform/dev-mec1723/Cargo.toml index 67aeb79..4b41a1e 100644 --- a/platform/dev-mec1723/Cargo.toml +++ b/platform/dev-mec1723/Cargo.toml @@ -51,7 +51,7 @@ embassy-executor = { version = "0.10.0", default-features = false, features = [ ] } embassy-microchip = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3", features = [ "defmt", - "mec1723n_b0_sz", # u_Note: the dev board i have with me says 'SZ' on it + "mec1723n_b0_sz", "rt", ] } uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-services", branch = "v0.2.0", features = [ diff --git a/platform/dev-mec1723/dev-mec1723.code-workspace b/platform/dev-mec1723/dev-mec1723.code-workspace index 49244a1..f527e93 100644 --- a/platform/dev-mec1723/dev-mec1723.code-workspace +++ b/platform/dev-mec1723/dev-mec1723.code-workspace @@ -9,7 +9,7 @@ ], "settings": { "rust-analyzer.checkOnSave": true, - "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", // u_Note: I chose this target because it's what the `mec17xx-pac` repo uses + "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", "rust-analyzer.linkedProjects": [ "platform/dev-mec1723/Cargo.toml" ], diff --git a/platform/dev-mec1723/link_ram.x b/platform/dev-mec1723/link_ram.x new file mode 100644 index 0000000..7ce8dbb --- /dev/null +++ b/platform/dev-mec1723/link_ram.x @@ -0,0 +1,280 @@ +/* ##### EMBASSY NOTE + Originally from https://github.com/rust-embedded/cortex-m/blob/master/cortex-m-rt/link.x.in + Adjusted to put everything in RAM +*/ + +/* # Developer notes + +- Symbols that start with a double underscore (__) are considered "private" + +- Symbols that start with a single underscore (_) are considered "semi-public"; they can be + overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" { + static mut __sbss }`). + +- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a + symbol if not dropped if it appears in or near the front of the linker arguments and "it's not + needed" by any of the preceding objects (linker arguments) + +- `PROVIDE` is used to provide default values that can be overridden by a user linker script + +- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and* + the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization + routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see + "Address (..) is out of bounds" in the disassembly produced by `objdump`. +*/ + +/* Provides information about the memory layout of the device */ +/* This will be provided by the user (see `memory.x`) or by a Board Support Crate */ +INCLUDE memory.x + +/* # Entry point = reset vector */ +EXTERN(__RESET_VECTOR); +EXTERN(Reset); +ENTRY(Reset); + +/* # Exception vectors */ +/* This is effectively weak aliasing at the linker level */ +/* The user can override any of these aliases by defining the corresponding symbol themselves (cf. + the `exception!` macro) */ +EXTERN(__EXCEPTIONS); /* depends on all the these PROVIDED symbols */ + +EXTERN(DefaultHandler); + +PROVIDE(NonMaskableInt = DefaultHandler); +EXTERN(HardFaultTrampoline); +PROVIDE(MemoryManagement = DefaultHandler); +PROVIDE(BusFault = DefaultHandler); +PROVIDE(UsageFault = DefaultHandler); +PROVIDE(SecureFault = DefaultHandler); +PROVIDE(SVCall = DefaultHandler); +PROVIDE(DebugMonitor = DefaultHandler); +PROVIDE(PendSV = DefaultHandler); +PROVIDE(SysTick = DefaultHandler); + +PROVIDE(DefaultHandler = DefaultHandler_); +PROVIDE(HardFault = HardFault_); + +/* # Interrupt vectors */ +EXTERN(__INTERRUPTS); /* `static` variable similar to `__EXCEPTIONS` */ + +/* # Pre-initialization function */ +/* If the user overrides this using the `pre_init!` macro or by creating a `__pre_init` function, + then the function this points to will be called before the RAM is initialized. */ +PROVIDE(__pre_init = DefaultPreInit); + +/* # Sections */ +SECTIONS +{ + PROVIDE(_ram_start = ORIGIN(RAM)); + PROVIDE(_ram_end = ORIGIN(RAM) + LENGTH(RAM)); + PROVIDE(_stack_start = _ram_end); + + /* ## Sections in RAM */ + /* ### Vector table */ + .vector_table ORIGIN(RAM) : + { + __vector_table = .; + + /* Initial Stack Pointer (SP) value. + * We mask the bottom three bits to force 8-byte alignment. + * Despite having an assert for this later, it's possible that a separate + * linker script could override _stack_start after the assert is checked. + */ + LONG(_stack_start & 0xFFFFFFF8); + + /* Reset vector */ + KEEP(*(.vector_table.reset_vector)); /* this is the `__RESET_VECTOR` symbol */ + + /* Exceptions */ + __exceptions = .; /* start of exceptions */ + KEEP(*(.vector_table.exceptions)); /* this is the `__EXCEPTIONS` symbol */ + __eexceptions = .; /* end of exceptions */ + + /* Device specific interrupts */ + KEEP(*(.vector_table.interrupts)); /* this is the `__INTERRUPTS` symbol */ + } > RAM + + PROVIDE(_stext = ADDR(.vector_table) + SIZEOF(.vector_table)); + + /* ### .text */ + .text _stext : + { + __stext = .; + *(.Reset); + + *(.text .text.*); + + /* The HardFaultTrampoline uses the `b` instruction to enter `HardFault`, + so must be placed close to it. */ + *(.HardFaultTrampoline); + *(.HardFault.*); + + . = ALIGN(4); /* Pad .text to the alignment to workaround overlapping load section bug in old lld */ + __etext = .; + } > RAM + + /* ### .rodata */ + .rodata : ALIGN(4) + { + . = ALIGN(4); + __srodata = .; + *(.rodata .rodata.*); + + /* 4-byte align the end (VMA) of this section. + This is required by LLD to ensure the LMA of the following .data + section will have the correct alignment. */ + . = ALIGN(4); + __erodata = .; + } > RAM + + /* ## Sections in RAM */ + /* ### .data */ + .data : ALIGN(4) + { + . = ALIGN(4); + __sdata = .; + __edata = .; /* RAM: By setting __sdata=__edata cortex-m-rt has to copy 0 bytes as .data is already in RAM */ + + *(.data .data.*); + . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ + } > RAM + /* Allow sections from user `memory.x` injected using `INSERT AFTER .data` to + * use the .data loading mechanism by pushing __edata. Note: do not change + * output region or load region in those user sections! */ + /* Link from RAM: Disabled, now __sdata == __edata + . = ALIGN(4); + __edata = .; + */ + + /* LMA of .data */ + __sidata = LOADADDR(.data); + + /* ### .gnu.sgstubs + This section contains the TrustZone-M veneers put there by the Arm GNU linker. */ + /* Security Attribution Unit blocks must be 32 bytes aligned. */ + /* Note that this pads the RAM usage to 32 byte alignment. */ + .gnu.sgstubs : ALIGN(32) + { + . = ALIGN(32); + __veneer_base = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + } > RAM + /* Place `__veneer_limit` outside the `.gnu.sgstubs` section because veneers are + * always inserted last in the section, which would otherwise be _after_ the `__veneer_limit` symbol. + */ + . = ALIGN(32); + __veneer_limit = .; + + /* ### .bss */ + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __sbss = .; + *(.bss .bss.*); + *(COMMON); /* Uninitialized C statics */ + . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ + } > RAM + /* Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to + * use the .bss zeroing mechanism by pushing __ebss. Note: do not change + * output region or load region in those user sections! */ + . = ALIGN(4); + __ebss = .; + + /* ### .uninit */ + .uninit (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __suninit = .; + *(.uninit .uninit.*); + . = ALIGN(4); + __euninit = .; + } > RAM + + /* Place the heap right after `.uninit` in RAM */ + PROVIDE(__sheap = __euninit); + + /* ## .got */ + /* Dynamic relocations are unsupported. This section is only used to detect relocatable code in + the input files and raise an error if relocatable code is found */ + .got (NOLOAD) : + { + KEEP(*(.got .got.*)); + } + + /* ## Discarded sections */ + /DISCARD/ : + { + /* Unused exception related info that only wastes space */ + *(.ARM.exidx); + *(.ARM.exidx.*); + *(.ARM.extab.*); + } +} + +/* Do not exceed this mark in the error messages below | */ +/* # Alignment checks */ +ASSERT(ORIGIN(RAM) % 4 == 0, " +ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned"); + +ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, " +BUG(cortex-m-rt): .data is not 4-byte aligned"); + +ASSERT(__sidata % 4 == 0, " +BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned"); + +ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, " +BUG(cortex-m-rt): .bss is not 4-byte aligned"); + +ASSERT(__sheap % 4 == 0, " +BUG(cortex-m-rt): start of .heap is not 4-byte aligned"); + +ASSERT(_stack_start % 8 == 0, " +ERROR(cortex-m-rt): stack start address is not 8-byte aligned. +If you have set _stack_start, check it's set to an address which is a multiple of 8 bytes. +If you haven't, stack starts at the end of RAM by default. Check that both RAM +origin and length are set to multiples of 8 in the `memory.x` file."); + +/* # Position checks */ + +/* ## .vector_table + * + * If the *start* of exception vectors is not 8 bytes past the start of the + * vector table, then we somehow did not place the reset vector, which should + * live 4 bytes past the start of the vector table. + */ +ASSERT(__exceptions == ADDR(.vector_table) + 0x8, " +BUG(cortex-m-rt): the reset vector is missing"); + +ASSERT(__eexceptions == ADDR(.vector_table) + 0x40, " +BUG(cortex-m-rt): the exception vectors are missing"); + +ASSERT(SIZEOF(.vector_table) > 0x40, " +ERROR(cortex-m-rt): The interrupt vectors are missing. +Possible solutions, from most likely to less likely: +- Link to a svd2rust generated device crate +- Check that you actually use the device/hal/bsp crate in your code +- Disable the 'device' feature of cortex-m-rt to build a generic application (a dependency +may be enabling it) +- Supply the interrupt handlers yourself. Check the documentation for details."); + +/* ## .text */ +ASSERT(ADDR(.vector_table) + SIZEOF(.vector_table) <= _stext, " +ERROR(cortex-m-rt): The .text section can't be placed inside the .vector_table section +Set _stext to an address greater than the end of .vector_table (See output of `nm`)"); + +ASSERT(_stext + SIZEOF(.text) < ORIGIN(RAM) + LENGTH(RAM), " +ERROR(cortex-m-rt): The .text section must be placed inside the RAM memory. +Set _stext to an address smaller than 'ORIGIN(RAM) + LENGTH(RAM)'"); + +/* # Other checks */ +ASSERT(SIZEOF(.got) == 0, " +ERROR(cortex-m-rt): .got section detected in the input object files +Dynamic relocations are not supported. If you are linking to C code compiled using +the 'cc' crate then modify your build script to compile the C code _without_ +the -fPIC flag. See the documentation of the `cc::Build.pic` method for details."); +/* Do not exceed this mark in the error messages above | */ + +/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */ +/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */ +INCLUDE device.x \ No newline at end of file diff --git a/platform/dev-mec1723/mec1723_custom.yaml b/platform/dev-mec1723/mec1723_custom.yaml deleted file mode 100644 index f831577..0000000 --- a/platform/dev-mec1723/mec1723_custom.yaml +++ /dev/null @@ -1,46 +0,0 @@ -name: Microchip MEC17xx Series Custom -generated_from_pack: true -pack_file_release: 1.4.221 -variants: -- name: MEC1723N_B0_SZ_CUSTOM - cores: - - name: main - type: armv7em - core_access_options: !Arm - ap: !v1 0 - memory_map: - - !Ram - name: IRAM1 - range: - start: 0xc0000 - end: 0x118000 - cores: - - main - - !Ram - name: IRAM2 - range: - start: 0x118000 - end: 0x128000 - cores: - - main - - !Generic - name: IRAM3 - range: - start: 0x20000000 - end: 0x20008000 - cores: - - main - - !Generic - name: IRAM4 - range: - start: 0x40100000 - end: 0x40106000 - cores: - - main - - !Nvm - name: EXTFLASH - range: - start: 0x50000000 - end: 0x58000000 - cores: - - main diff --git a/platform/dev-mec1723/memory.x b/platform/dev-mec1723/memory.x index 3d94b2a..0933d2f 100644 --- a/platform/dev-mec1723/memory.x +++ b/platform/dev-mec1723/memory.x @@ -1,12 +1,3 @@ MEMORY { - /* - u_Notes about FLASH: - - This assumes the 'Cache SPI Enable' bit is 0, which it is by default. - - See FIGURE 7-1 on page 180 of the datasheet for more info (384KB comes from 32KB + 352KB. If the 'Cache SPI Enable' bit was 1, FLASH would just be 352KB). - - ^^ Datasheet for the chip: https://www.microchip.com/content/dam/mchp/documents/CPG/ProductDocuments/DataSheets/MEC172x-Data-Sheet-DS00003583E.pdf - - Also, the 384K number is supported by https://github.com/embassy-rs/embassy/blob/e9c32931b906649d65fc502fe8e8f2c70ef1e6ab/examples/microchip/memory.x - */ - FLASH : ORIGIN = 0x000C0000, LENGTH = 384K - - RAM : ORIGIN = 0x00118000, LENGTH = 62K + RAM : ORIGIN = 0x000c0000, LENGTH = 384K } \ No newline at end of file From 65af216061ba7c67356a5716dfb5053417d82d29 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Tue, 26 May 2026 11:11:06 -0700 Subject: [PATCH 13/15] renamed to dev-mec, changed Cargo.toml dependency branches --- platform/dev-mec/.cargo/config.toml | 17 + platform/dev-mec/Cargo.lock | 1453 +++++++++++++++++++++++ platform/dev-mec/Cargo.toml | 81 ++ platform/dev-mec/build.rs | 22 + platform/dev-mec/dev-mec.code-workspace | 23 + platform/dev-mec/link_ram.x | 280 +++++ platform/dev-mec/memory.x | 3 + platform/dev-mec/src/board.rs | 32 + platform/dev-mec/src/main.rs | 37 + 9 files changed, 1948 insertions(+) create mode 100644 platform/dev-mec/.cargo/config.toml create mode 100644 platform/dev-mec/Cargo.lock create mode 100644 platform/dev-mec/Cargo.toml create mode 100644 platform/dev-mec/build.rs create mode 100644 platform/dev-mec/dev-mec.code-workspace create mode 100644 platform/dev-mec/link_ram.x create mode 100644 platform/dev-mec/memory.x create mode 100644 platform/dev-mec/src/board.rs create mode 100644 platform/dev-mec/src/main.rs diff --git a/platform/dev-mec/.cargo/config.toml b/platform/dev-mec/.cargo/config.toml new file mode 100644 index 0000000..f1cc30c --- /dev/null +++ b/platform/dev-mec/.cargo/config.toml @@ -0,0 +1,17 @@ +[target.thumbv7em-none-eabihf] +runner = 'probe-rs run --chip MEC1723N_B0_SZ' + +rustflags = [ + # "-C", "linker=flip-link", + "-C", "link-arg=-Tlink_ram.x", + "-C", "link-arg=-Tdefmt.x", + # This is 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= { version = "0.10.0", default-features = false, features = [ + "platform-cortex-m", + "executor-thread", + "executor-interrupt", + "defmt", +] } +embassy-microchip = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy", features = [ + "defmt", + "mec1723n_b0_sz", + "rt", +] } +uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-services", branch = "v0.2.0", features = [ + "defmt", +] } +static_cell = "2.1.0" +embassy-time = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embedded-hal = "0.2" +platform-common = { path = "../platform-common", features = ["mock"] } +panic-probe = { version = "1.0.0", features = ["print-defmt"] } + +[package.metadata.cargo-machete] +ignored = ["cortex-m", "cortex-m-rt"] + +# embassy-microchip pulls embassy-time-driver from the embassy-rs git repo, which +# uses `links = "embassy-time"`. Other crates in the dependency graph pull +# embassy-time/embassy-time-driver from crates.io, which would cause a duplicate +# `links` conflict. Force everyone to use the git versions. +[patch.crates-io] +embassy-time = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-time-driver = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-time-queue-utils = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-sync = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-executor = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-futures = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-embedded-hal = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } +embassy-hal-internal = { git = "https://github.com/bjackson312006/embassy", branch = "microchip-uart-buffer-hack.update-embassy" } diff --git a/platform/dev-mec/build.rs b/platform/dev-mec/build.rs new file mode 100644 index 0000000..94135b4 --- /dev/null +++ b/platform/dev-mec/build.rs @@ -0,0 +1,22 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; + +fn main() { + // Put `memory.x` in our output directory and ensure it's + // on the linker search path. + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("memory.x")) + .unwrap() + .write_all(include_bytes!("memory.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + + // By default, Cargo will re-run a build script whenever + // any file in the project changes. By specifying `memory.x` and 'link_ram.x' + // here, we ensure the build script is only re-run when + // `memory.x` or 'link_ram.x' is changed. + println!("cargo:rerun-if-changed=memory.x"); + println!("cargo:rerun-if-changed=link_ram.x"); +} diff --git a/platform/dev-mec/dev-mec.code-workspace b/platform/dev-mec/dev-mec.code-workspace new file mode 100644 index 0000000..96e03cb --- /dev/null +++ b/platform/dev-mec/dev-mec.code-workspace @@ -0,0 +1,23 @@ +{ + "folders": [ + { + "path": "../.." + }, + { + "path": "." + } + ], + "settings": { + "rust-analyzer.checkOnSave": true, + "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", + "rust-analyzer.linkedProjects": [ + "platform/dev-mec/Cargo.toml" + ], + "rust-analyzer.check.workspace": false, + "terminal.integrated.cwd": ".", + // + // Variables for launch.json customization + // (grayed out in UI, but can be used in launch.json) + "platform": "dev-mec", + }, +} \ No newline at end of file diff --git a/platform/dev-mec/link_ram.x b/platform/dev-mec/link_ram.x new file mode 100644 index 0000000..7ce8dbb --- /dev/null +++ b/platform/dev-mec/link_ram.x @@ -0,0 +1,280 @@ +/* ##### EMBASSY NOTE + Originally from https://github.com/rust-embedded/cortex-m/blob/master/cortex-m-rt/link.x.in + Adjusted to put everything in RAM +*/ + +/* # Developer notes + +- Symbols that start with a double underscore (__) are considered "private" + +- Symbols that start with a single underscore (_) are considered "semi-public"; they can be + overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" { + static mut __sbss }`). + +- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a + symbol if not dropped if it appears in or near the front of the linker arguments and "it's not + needed" by any of the preceding objects (linker arguments) + +- `PROVIDE` is used to provide default values that can be overridden by a user linker script + +- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and* + the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization + routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see + "Address (..) is out of bounds" in the disassembly produced by `objdump`. +*/ + +/* Provides information about the memory layout of the device */ +/* This will be provided by the user (see `memory.x`) or by a Board Support Crate */ +INCLUDE memory.x + +/* # Entry point = reset vector */ +EXTERN(__RESET_VECTOR); +EXTERN(Reset); +ENTRY(Reset); + +/* # Exception vectors */ +/* This is effectively weak aliasing at the linker level */ +/* The user can override any of these aliases by defining the corresponding symbol themselves (cf. + the `exception!` macro) */ +EXTERN(__EXCEPTIONS); /* depends on all the these PROVIDED symbols */ + +EXTERN(DefaultHandler); + +PROVIDE(NonMaskableInt = DefaultHandler); +EXTERN(HardFaultTrampoline); +PROVIDE(MemoryManagement = DefaultHandler); +PROVIDE(BusFault = DefaultHandler); +PROVIDE(UsageFault = DefaultHandler); +PROVIDE(SecureFault = DefaultHandler); +PROVIDE(SVCall = DefaultHandler); +PROVIDE(DebugMonitor = DefaultHandler); +PROVIDE(PendSV = DefaultHandler); +PROVIDE(SysTick = DefaultHandler); + +PROVIDE(DefaultHandler = DefaultHandler_); +PROVIDE(HardFault = HardFault_); + +/* # Interrupt vectors */ +EXTERN(__INTERRUPTS); /* `static` variable similar to `__EXCEPTIONS` */ + +/* # Pre-initialization function */ +/* If the user overrides this using the `pre_init!` macro or by creating a `__pre_init` function, + then the function this points to will be called before the RAM is initialized. */ +PROVIDE(__pre_init = DefaultPreInit); + +/* # Sections */ +SECTIONS +{ + PROVIDE(_ram_start = ORIGIN(RAM)); + PROVIDE(_ram_end = ORIGIN(RAM) + LENGTH(RAM)); + PROVIDE(_stack_start = _ram_end); + + /* ## Sections in RAM */ + /* ### Vector table */ + .vector_table ORIGIN(RAM) : + { + __vector_table = .; + + /* Initial Stack Pointer (SP) value. + * We mask the bottom three bits to force 8-byte alignment. + * Despite having an assert for this later, it's possible that a separate + * linker script could override _stack_start after the assert is checked. + */ + LONG(_stack_start & 0xFFFFFFF8); + + /* Reset vector */ + KEEP(*(.vector_table.reset_vector)); /* this is the `__RESET_VECTOR` symbol */ + + /* Exceptions */ + __exceptions = .; /* start of exceptions */ + KEEP(*(.vector_table.exceptions)); /* this is the `__EXCEPTIONS` symbol */ + __eexceptions = .; /* end of exceptions */ + + /* Device specific interrupts */ + KEEP(*(.vector_table.interrupts)); /* this is the `__INTERRUPTS` symbol */ + } > RAM + + PROVIDE(_stext = ADDR(.vector_table) + SIZEOF(.vector_table)); + + /* ### .text */ + .text _stext : + { + __stext = .; + *(.Reset); + + *(.text .text.*); + + /* The HardFaultTrampoline uses the `b` instruction to enter `HardFault`, + so must be placed close to it. */ + *(.HardFaultTrampoline); + *(.HardFault.*); + + . = ALIGN(4); /* Pad .text to the alignment to workaround overlapping load section bug in old lld */ + __etext = .; + } > RAM + + /* ### .rodata */ + .rodata : ALIGN(4) + { + . = ALIGN(4); + __srodata = .; + *(.rodata .rodata.*); + + /* 4-byte align the end (VMA) of this section. + This is required by LLD to ensure the LMA of the following .data + section will have the correct alignment. */ + . = ALIGN(4); + __erodata = .; + } > RAM + + /* ## Sections in RAM */ + /* ### .data */ + .data : ALIGN(4) + { + . = ALIGN(4); + __sdata = .; + __edata = .; /* RAM: By setting __sdata=__edata cortex-m-rt has to copy 0 bytes as .data is already in RAM */ + + *(.data .data.*); + . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ + } > RAM + /* Allow sections from user `memory.x` injected using `INSERT AFTER .data` to + * use the .data loading mechanism by pushing __edata. Note: do not change + * output region or load region in those user sections! */ + /* Link from RAM: Disabled, now __sdata == __edata + . = ALIGN(4); + __edata = .; + */ + + /* LMA of .data */ + __sidata = LOADADDR(.data); + + /* ### .gnu.sgstubs + This section contains the TrustZone-M veneers put there by the Arm GNU linker. */ + /* Security Attribution Unit blocks must be 32 bytes aligned. */ + /* Note that this pads the RAM usage to 32 byte alignment. */ + .gnu.sgstubs : ALIGN(32) + { + . = ALIGN(32); + __veneer_base = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + } > RAM + /* Place `__veneer_limit` outside the `.gnu.sgstubs` section because veneers are + * always inserted last in the section, which would otherwise be _after_ the `__veneer_limit` symbol. + */ + . = ALIGN(32); + __veneer_limit = .; + + /* ### .bss */ + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __sbss = .; + *(.bss .bss.*); + *(COMMON); /* Uninitialized C statics */ + . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ + } > RAM + /* Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to + * use the .bss zeroing mechanism by pushing __ebss. Note: do not change + * output region or load region in those user sections! */ + . = ALIGN(4); + __ebss = .; + + /* ### .uninit */ + .uninit (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __suninit = .; + *(.uninit .uninit.*); + . = ALIGN(4); + __euninit = .; + } > RAM + + /* Place the heap right after `.uninit` in RAM */ + PROVIDE(__sheap = __euninit); + + /* ## .got */ + /* Dynamic relocations are unsupported. This section is only used to detect relocatable code in + the input files and raise an error if relocatable code is found */ + .got (NOLOAD) : + { + KEEP(*(.got .got.*)); + } + + /* ## Discarded sections */ + /DISCARD/ : + { + /* Unused exception related info that only wastes space */ + *(.ARM.exidx); + *(.ARM.exidx.*); + *(.ARM.extab.*); + } +} + +/* Do not exceed this mark in the error messages below | */ +/* # Alignment checks */ +ASSERT(ORIGIN(RAM) % 4 == 0, " +ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned"); + +ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, " +BUG(cortex-m-rt): .data is not 4-byte aligned"); + +ASSERT(__sidata % 4 == 0, " +BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned"); + +ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, " +BUG(cortex-m-rt): .bss is not 4-byte aligned"); + +ASSERT(__sheap % 4 == 0, " +BUG(cortex-m-rt): start of .heap is not 4-byte aligned"); + +ASSERT(_stack_start % 8 == 0, " +ERROR(cortex-m-rt): stack start address is not 8-byte aligned. +If you have set _stack_start, check it's set to an address which is a multiple of 8 bytes. +If you haven't, stack starts at the end of RAM by default. Check that both RAM +origin and length are set to multiples of 8 in the `memory.x` file."); + +/* # Position checks */ + +/* ## .vector_table + * + * If the *start* of exception vectors is not 8 bytes past the start of the + * vector table, then we somehow did not place the reset vector, which should + * live 4 bytes past the start of the vector table. + */ +ASSERT(__exceptions == ADDR(.vector_table) + 0x8, " +BUG(cortex-m-rt): the reset vector is missing"); + +ASSERT(__eexceptions == ADDR(.vector_table) + 0x40, " +BUG(cortex-m-rt): the exception vectors are missing"); + +ASSERT(SIZEOF(.vector_table) > 0x40, " +ERROR(cortex-m-rt): The interrupt vectors are missing. +Possible solutions, from most likely to less likely: +- Link to a svd2rust generated device crate +- Check that you actually use the device/hal/bsp crate in your code +- Disable the 'device' feature of cortex-m-rt to build a generic application (a dependency +may be enabling it) +- Supply the interrupt handlers yourself. Check the documentation for details."); + +/* ## .text */ +ASSERT(ADDR(.vector_table) + SIZEOF(.vector_table) <= _stext, " +ERROR(cortex-m-rt): The .text section can't be placed inside the .vector_table section +Set _stext to an address greater than the end of .vector_table (See output of `nm`)"); + +ASSERT(_stext + SIZEOF(.text) < ORIGIN(RAM) + LENGTH(RAM), " +ERROR(cortex-m-rt): The .text section must be placed inside the RAM memory. +Set _stext to an address smaller than 'ORIGIN(RAM) + LENGTH(RAM)'"); + +/* # Other checks */ +ASSERT(SIZEOF(.got) == 0, " +ERROR(cortex-m-rt): .got section detected in the input object files +Dynamic relocations are not supported. If you are linking to C code compiled using +the 'cc' crate then modify your build script to compile the C code _without_ +the -fPIC flag. See the documentation of the `cc::Build.pic` method for details."); +/* Do not exceed this mark in the error messages above | */ + +/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */ +/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */ +INCLUDE device.x \ No newline at end of file diff --git a/platform/dev-mec/memory.x b/platform/dev-mec/memory.x new file mode 100644 index 0000000..0933d2f --- /dev/null +++ b/platform/dev-mec/memory.x @@ -0,0 +1,3 @@ +MEMORY { + RAM : ORIGIN = 0x000c0000, LENGTH = 384K +} \ No newline at end of file diff --git a/platform/dev-mec/src/board.rs b/platform/dev-mec/src/board.rs new file mode 100644 index 0000000..76a17ce --- /dev/null +++ b/platform/dev-mec/src/board.rs @@ -0,0 +1,32 @@ +use platform_common::board::BoardIo; +use embassy_microchip::{uart, bind_interrupts, peripherals, Peripherals}; +use static_cell::ConstStaticCell; + +bind_interrupts!(struct Irqs { + UART1 => uart::InterruptHandler::; +}); + +static UART_BUFFER: ConstStaticCell<[u8; 1024]> = ConstStaticCell::new([0u8; 1024]); + +/// Board IO for the dev-mec platform. +pub struct Board { + pub uart: uart::Uart<'static, uart::Async>, +} + +impl BoardIo for Board { + type Peripherals = Peripherals; + + fn init(p: Self::Peripherals) -> Self { + Board { + /* Set up async UART */ + uart: uart::Uart::new_async( + p.UART1, + p.GPIO171, + p.GPIO170, + Irqs, + UART_BUFFER.take(), + uart::Config::default() + ).expect("Failed to create 'uart' in 'Board'.") + } + } +} diff --git a/platform/dev-mec/src/main.rs b/platform/dev-mec/src/main.rs new file mode 100644 index 0000000..f4296e3 --- /dev/null +++ b/platform/dev-mec/src/main.rs @@ -0,0 +1,37 @@ +#![no_std] +#![no_main] + +mod board; + +use board::Board; +use defmt::info; +use defmt_rtt as _; +use embassy_executor::Spawner; +use embassy_microchip::uart; +use panic_probe as _; +use platform_common::board::BoardIo; +use platform_common::mock::MockOdpRelayHandler; +use static_cell::StaticCell; + +#[embassy_executor::task] +async fn uart_service(uart: uart::Uart<'static, uart::Async>, relay: MockOdpRelayHandler) { + info!("Starting uart service"); + static UART_SERVICE: StaticCell> = StaticCell::new(); + let uart_service = uart_service::DefaultService::default_smbusespi(relay).unwrap(); + let uart_service = UART_SERVICE.init(uart_service); + + let Err(e) = uart_service::task::uart_service(uart_service, uart).await; + panic!("uart-service error: {:?}", e); +} + +#[embassy_executor::main] +async fn main(spawner: Spawner) { + info!("Booting..."); + let p = embassy_microchip::init(embassy_microchip::config::Config::default()); + let board = Board::init(p); + + info!("Hello world from MEC1723!"); + + let relay = platform_common::mock::init(spawner).await; + spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); +} \ No newline at end of file From ce79c84aa77acbdd8319685ce14b643907d5794c Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Tue, 26 May 2026 11:38:10 -0700 Subject: [PATCH 14/15] update deleted files on gh? --- platform/dev-mec1723/.cargo/config.toml | 17 - platform/dev-mec1723/.gitignore | 2 - platform/dev-mec1723/Cargo.lock | 1453 ----------------- platform/dev-mec1723/Cargo.toml | 81 - platform/dev-mec1723/build.rs | 21 - .../dev-mec1723/dev-mec1723.code-workspace | 23 - platform/dev-mec1723/link_ram.x | 280 ---- platform/dev-mec1723/memory.x | 3 - platform/dev-mec1723/src/board.rs | 32 - platform/dev-mec1723/src/main.rs | 37 - 10 files changed, 1949 deletions(-) delete mode 100644 platform/dev-mec1723/.cargo/config.toml delete mode 100644 platform/dev-mec1723/.gitignore delete mode 100644 platform/dev-mec1723/Cargo.lock delete mode 100644 platform/dev-mec1723/Cargo.toml delete mode 100644 platform/dev-mec1723/build.rs delete mode 100644 platform/dev-mec1723/dev-mec1723.code-workspace delete mode 100644 platform/dev-mec1723/link_ram.x delete mode 100644 platform/dev-mec1723/memory.x delete mode 100644 platform/dev-mec1723/src/board.rs delete mode 100644 platform/dev-mec1723/src/main.rs diff --git a/platform/dev-mec1723/.cargo/config.toml b/platform/dev-mec1723/.cargo/config.toml deleted file mode 100644 index f1cc30c..0000000 --- a/platform/dev-mec1723/.cargo/config.toml +++ /dev/null @@ -1,17 +0,0 @@ -[target.thumbv7em-none-eabihf] -runner = 'probe-rs run --chip MEC1723N_B0_SZ' - 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-[[bin]] -bench = false -name = "dev-mec1723" -test = false - -[profile.release] -lto = true # better optimizations -codegen-units = 1 -debug = true -opt-level = "z" -panic = "abort" -incremental = false - -# Optimize dependencies for size but keep root crate unoptimized for better debuggability -[profile.dev.package."*"] -opt-level = "z" - -# Uncomment to turn off optimization for specific dependency (such as when debugging a service) -# [profile.dev.package.dependency-name] -# opt-level = 0 - -[lints.rust] -warnings = "deny" - -[lints.clippy] -correctness = "deny" -perf = "deny" -suspicious = "deny" -style = "deny" - -[dependencies] -cortex-m = { version = "0.7.7", features = [ - "inline-asm", - "critical-section-single-core", -] } -cortex-m-rt = { version = "0.7.3", features = ["device"] } -defmt = "1.0" -defmt-rtt = "1.0" -embassy-executor = { version = "0.10.0", default-features = false, features = [ - "platform-cortex-m", - "executor-thread", - "executor-interrupt", - "defmt", -] } -embassy-microchip = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3", features = [ - "defmt", - "mec1723n_b0_sz", - "rt", -] } -uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-services", branch = "v0.2.0", features = [ - "defmt", -] } -static_cell = "2.1.0" -embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embedded-hal = "0.2" -platform-common = { path = "../platform-common", features = ["mock"] } -panic-probe = { version = "1.0.0", features = ["print-defmt"] } - -[package.metadata.cargo-machete] -ignored = ["cortex-m", "cortex-m-rt"] - -# embassy-microchip pulls embassy-time-driver from the embassy-rs git repo, which -# uses `links = "embassy-time"`. Other crates in the dependency graph pull -# embassy-time/embassy-time-driver from crates.io, which would cause a duplicate -# `links` conflict. Force everyone to use the git versions. -[patch.crates-io] -embassy-time = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-time-driver = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-time-queue-utils = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-sync = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-executor = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-futures = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-embedded-hal = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } -embassy-hal-internal = { git = "https://github.com/bjackson312006/embassy", rev = "e85b387cf915241a1d9e0ba32ab4a7a1117896b3" } diff --git a/platform/dev-mec1723/build.rs b/platform/dev-mec1723/build.rs deleted file mode 100644 index 555cdf6..0000000 --- a/platform/dev-mec1723/build.rs +++ /dev/null @@ -1,21 +0,0 @@ -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; - -fn main() { - // Put `memory.x` in our output directory and ensure it's - // on the linker search path. - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - File::create(out.join("memory.x")) - .unwrap() - .write_all(include_bytes!("memory.x")) - .unwrap(); - println!("cargo:rustc-link-search={}", out.display()); - - // By default, Cargo will re-run a build script whenever - // any file in the project changes. By specifying `memory.x` - // here, we ensure the build script is only re-run when - // `memory.x` is changed. - println!("cargo:rerun-if-changed=memory.x"); -} diff --git a/platform/dev-mec1723/dev-mec1723.code-workspace b/platform/dev-mec1723/dev-mec1723.code-workspace deleted file mode 100644 index f527e93..0000000 --- a/platform/dev-mec1723/dev-mec1723.code-workspace +++ /dev/null @@ -1,23 +0,0 @@ -{ - "folders": [ - { - "path": "../.." - }, - { - "path": "." - } - ], - "settings": { - "rust-analyzer.checkOnSave": true, - "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", - "rust-analyzer.linkedProjects": [ - "platform/dev-mec1723/Cargo.toml" - ], - "rust-analyzer.check.workspace": false, - "terminal.integrated.cwd": ".", - // - // Variables for launch.json customization - // (grayed out in UI, but can be used in launch.json) - "platform": "dev-mec1723", - }, -} \ No newline at end of file diff --git a/platform/dev-mec1723/link_ram.x b/platform/dev-mec1723/link_ram.x deleted file mode 100644 index 7ce8dbb..0000000 --- a/platform/dev-mec1723/link_ram.x +++ /dev/null @@ -1,280 +0,0 @@ -/* ##### EMBASSY NOTE - Originally from https://github.com/rust-embedded/cortex-m/blob/master/cortex-m-rt/link.x.in - Adjusted to put everything in RAM -*/ - -/* # Developer notes - -- Symbols that start with a double underscore (__) are considered "private" - -- Symbols that start with a single underscore (_) are considered "semi-public"; they can be - overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" { - static mut __sbss }`). - -- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a - symbol if not dropped if it appears in or near the front of the linker arguments and "it's not - needed" by any of the preceding objects (linker arguments) - -- `PROVIDE` is used to provide default values that can be overridden by a user linker script - -- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and* - the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization - routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see - "Address (..) is out of bounds" in the disassembly produced by `objdump`. -*/ - -/* Provides information about the memory layout of the device */ -/* This will be provided by the user (see `memory.x`) or by a Board Support Crate */ -INCLUDE memory.x - -/* # Entry point = reset vector */ -EXTERN(__RESET_VECTOR); -EXTERN(Reset); -ENTRY(Reset); - -/* # Exception vectors */ -/* This is effectively weak aliasing at the linker level */ -/* The user can override any of these aliases by defining the corresponding symbol themselves (cf. - the `exception!` macro) */ -EXTERN(__EXCEPTIONS); /* depends on all the these PROVIDED symbols */ - -EXTERN(DefaultHandler); - -PROVIDE(NonMaskableInt = DefaultHandler); -EXTERN(HardFaultTrampoline); -PROVIDE(MemoryManagement = DefaultHandler); -PROVIDE(BusFault = DefaultHandler); -PROVIDE(UsageFault = DefaultHandler); -PROVIDE(SecureFault = DefaultHandler); -PROVIDE(SVCall = DefaultHandler); -PROVIDE(DebugMonitor = DefaultHandler); -PROVIDE(PendSV = DefaultHandler); -PROVIDE(SysTick = DefaultHandler); - -PROVIDE(DefaultHandler = DefaultHandler_); -PROVIDE(HardFault = HardFault_); - -/* # Interrupt vectors */ -EXTERN(__INTERRUPTS); /* `static` variable similar to `__EXCEPTIONS` */ - -/* # Pre-initialization function */ -/* If the user overrides this using the `pre_init!` macro or by creating a `__pre_init` function, - then the function this points to will be called before the RAM is initialized. */ -PROVIDE(__pre_init = DefaultPreInit); - -/* # Sections */ -SECTIONS -{ - PROVIDE(_ram_start = ORIGIN(RAM)); - PROVIDE(_ram_end = ORIGIN(RAM) + LENGTH(RAM)); - PROVIDE(_stack_start = _ram_end); - - /* ## Sections in RAM */ - /* ### Vector table */ - .vector_table ORIGIN(RAM) : - { - __vector_table = .; - - /* Initial Stack Pointer (SP) value. - * We mask the bottom three bits to force 8-byte alignment. - * Despite having an assert for this later, it's possible that a separate - * linker script could override _stack_start after the assert is checked. - */ - LONG(_stack_start & 0xFFFFFFF8); - - /* Reset vector */ - KEEP(*(.vector_table.reset_vector)); /* this is the `__RESET_VECTOR` symbol */ - - /* Exceptions */ - __exceptions = .; /* start of exceptions */ - KEEP(*(.vector_table.exceptions)); /* this is the `__EXCEPTIONS` symbol */ - __eexceptions = .; /* end of exceptions */ - - /* Device specific interrupts */ - KEEP(*(.vector_table.interrupts)); /* this is the `__INTERRUPTS` symbol */ - } > RAM - - PROVIDE(_stext = ADDR(.vector_table) + SIZEOF(.vector_table)); - - /* ### .text */ - .text _stext : - { - __stext = .; - *(.Reset); - - *(.text .text.*); - - /* The HardFaultTrampoline uses the `b` instruction to enter `HardFault`, - so must be placed close to it. */ - *(.HardFaultTrampoline); - *(.HardFault.*); - - . = ALIGN(4); /* Pad .text to the alignment to workaround overlapping load section bug in old lld */ - __etext = .; - } > RAM - - /* ### .rodata */ - .rodata : ALIGN(4) - { - . = ALIGN(4); - __srodata = .; - *(.rodata .rodata.*); - - /* 4-byte align the end (VMA) of this section. - This is required by LLD to ensure the LMA of the following .data - section will have the correct alignment. */ - . = ALIGN(4); - __erodata = .; - } > RAM - - /* ## Sections in RAM */ - /* ### .data */ - .data : ALIGN(4) - { - . = ALIGN(4); - __sdata = .; - __edata = .; /* RAM: By setting __sdata=__edata cortex-m-rt has to copy 0 bytes as .data is already in RAM */ - - *(.data .data.*); - . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ - } > RAM - /* Allow sections from user `memory.x` injected using `INSERT AFTER .data` to - * use the .data loading mechanism by pushing __edata. Note: do not change - * output region or load region in those user sections! */ - /* Link from RAM: Disabled, now __sdata == __edata - . = ALIGN(4); - __edata = .; - */ - - /* LMA of .data */ - __sidata = LOADADDR(.data); - - /* ### .gnu.sgstubs - This section contains the TrustZone-M veneers put there by the Arm GNU linker. */ - /* Security Attribution Unit blocks must be 32 bytes aligned. */ - /* Note that this pads the RAM usage to 32 byte alignment. */ - .gnu.sgstubs : ALIGN(32) - { - . = ALIGN(32); - __veneer_base = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - } > RAM - /* Place `__veneer_limit` outside the `.gnu.sgstubs` section because veneers are - * always inserted last in the section, which would otherwise be _after_ the `__veneer_limit` symbol. - */ - . = ALIGN(32); - __veneer_limit = .; - - /* ### .bss */ - .bss (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __sbss = .; - *(.bss .bss.*); - *(COMMON); /* Uninitialized C statics */ - . = ALIGN(4); /* 4-byte align the end (VMA) of this section */ - } > RAM - /* Allow sections from user `memory.x` injected using `INSERT AFTER .bss` to - * use the .bss zeroing mechanism by pushing __ebss. Note: do not change - * output region or load region in those user sections! */ - . = ALIGN(4); - __ebss = .; - - /* ### .uninit */ - .uninit (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __suninit = .; - *(.uninit .uninit.*); - . = ALIGN(4); - __euninit = .; - } > RAM - - /* Place the heap right after `.uninit` in RAM */ - PROVIDE(__sheap = __euninit); - - /* ## .got */ - /* Dynamic relocations are unsupported. This section is only used to detect relocatable code in - the input files and raise an error if relocatable code is found */ - .got (NOLOAD) : - { - KEEP(*(.got .got.*)); - } - - /* ## Discarded sections */ - /DISCARD/ : - { - /* Unused exception related info that only wastes space */ - *(.ARM.exidx); - *(.ARM.exidx.*); - *(.ARM.extab.*); - } -} - -/* Do not exceed this mark in the error messages below | */ -/* # Alignment checks */ -ASSERT(ORIGIN(RAM) % 4 == 0, " -ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned"); - -ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, " -BUG(cortex-m-rt): .data is not 4-byte aligned"); - -ASSERT(__sidata % 4 == 0, " -BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned"); - -ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, " -BUG(cortex-m-rt): .bss is not 4-byte aligned"); - -ASSERT(__sheap % 4 == 0, " -BUG(cortex-m-rt): start of .heap is not 4-byte aligned"); - -ASSERT(_stack_start % 8 == 0, " -ERROR(cortex-m-rt): stack start address is not 8-byte aligned. -If you have set _stack_start, check it's set to an address which is a multiple of 8 bytes. -If you haven't, stack starts at the end of RAM by default. Check that both RAM -origin and length are set to multiples of 8 in the `memory.x` file."); - -/* # Position checks */ - -/* ## .vector_table - * - * If the *start* of exception vectors is not 8 bytes past the start of the - * vector table, then we somehow did not place the reset vector, which should - * live 4 bytes past the start of the vector table. - */ -ASSERT(__exceptions == ADDR(.vector_table) + 0x8, " -BUG(cortex-m-rt): the reset vector is missing"); - -ASSERT(__eexceptions == ADDR(.vector_table) + 0x40, " -BUG(cortex-m-rt): the exception vectors are missing"); - -ASSERT(SIZEOF(.vector_table) > 0x40, " -ERROR(cortex-m-rt): The interrupt vectors are missing. -Possible solutions, from most likely to less likely: -- Link to a svd2rust generated device crate -- Check that you actually use the device/hal/bsp crate in your code -- Disable the 'device' feature of cortex-m-rt to build a generic application (a dependency -may be enabling it) -- Supply the interrupt handlers yourself. Check the documentation for details."); - -/* ## .text */ -ASSERT(ADDR(.vector_table) + SIZEOF(.vector_table) <= _stext, " -ERROR(cortex-m-rt): The .text section can't be placed inside the .vector_table section -Set _stext to an address greater than the end of .vector_table (See output of `nm`)"); - -ASSERT(_stext + SIZEOF(.text) < ORIGIN(RAM) + LENGTH(RAM), " -ERROR(cortex-m-rt): The .text section must be placed inside the RAM memory. -Set _stext to an address smaller than 'ORIGIN(RAM) + LENGTH(RAM)'"); - -/* # Other checks */ -ASSERT(SIZEOF(.got) == 0, " -ERROR(cortex-m-rt): .got section detected in the input object files -Dynamic relocations are not supported. If you are linking to C code compiled using -the 'cc' crate then modify your build script to compile the C code _without_ -the -fPIC flag. See the documentation of the `cc::Build.pic` method for details."); -/* Do not exceed this mark in the error messages above | */ - -/* Provides weak aliases (cf. PROVIDED) for device specific interrupt handlers */ -/* This will usually be provided by a device crate generated using svd2rust (see `device.x`) */ -INCLUDE device.x \ No newline at end of file diff --git a/platform/dev-mec1723/memory.x b/platform/dev-mec1723/memory.x deleted file mode 100644 index 0933d2f..0000000 --- a/platform/dev-mec1723/memory.x +++ /dev/null @@ -1,3 +0,0 @@ -MEMORY { - RAM : ORIGIN = 0x000c0000, LENGTH = 384K -} \ No newline at end of file diff --git a/platform/dev-mec1723/src/board.rs b/platform/dev-mec1723/src/board.rs deleted file mode 100644 index 653abb8..0000000 --- a/platform/dev-mec1723/src/board.rs +++ /dev/null @@ -1,32 +0,0 @@ -use platform_common::board::BoardIo; -use embassy_microchip::{uart, bind_interrupts, peripherals, Peripherals}; -use static_cell::ConstStaticCell; - -bind_interrupts!(struct Irqs { - UART1 => uart::InterruptHandler::; -}); - -static UART_BUFFER: ConstStaticCell<[u8; 1024]> = ConstStaticCell::new([0u8; 1024]); - -/// Board IO for the dev-mec1723 platform. -pub struct Board { - pub uart: uart::Uart<'static, uart::Async>, -} - -impl BoardIo for Board { - type Peripherals = Peripherals; - - fn init(p: Self::Peripherals) -> Self { - Board { - /* Set up async UART on UART0 */ - uart: uart::Uart::new_async( - p.UART1, - p.GPIO171, - p.GPIO170, - Irqs, - UART_BUFFER.take(), - uart::Config::default() - ).expect("Failed to create 'uart' in 'Board'.") - } - } -} diff --git a/platform/dev-mec1723/src/main.rs b/platform/dev-mec1723/src/main.rs deleted file mode 100644 index f4296e3..0000000 --- a/platform/dev-mec1723/src/main.rs +++ /dev/null @@ -1,37 +0,0 @@ -#![no_std] -#![no_main] - -mod board; - -use board::Board; -use defmt::info; -use defmt_rtt as _; -use embassy_executor::Spawner; -use embassy_microchip::uart; -use panic_probe as _; -use platform_common::board::BoardIo; -use platform_common::mock::MockOdpRelayHandler; -use static_cell::StaticCell; - -#[embassy_executor::task] -async fn uart_service(uart: uart::Uart<'static, uart::Async>, relay: MockOdpRelayHandler) { - info!("Starting uart service"); - static UART_SERVICE: StaticCell> = StaticCell::new(); - let uart_service = uart_service::DefaultService::default_smbusespi(relay).unwrap(); - let uart_service = UART_SERVICE.init(uart_service); - - let Err(e) = uart_service::task::uart_service(uart_service, uart).await; - panic!("uart-service error: {:?}", e); -} - -#[embassy_executor::main] -async fn main(spawner: Spawner) { - info!("Booting..."); - let p = embassy_microchip::init(embassy_microchip::config::Config::default()); - let board = Board::init(p); - - info!("Hello world from MEC1723!"); - - let relay = platform_common::mock::init(spawner).await; - spawner.spawn(uart_service(board.uart, relay).expect("Failed to spawn UART service task")); -} \ No newline at end of file From 132162391f1a167a73ee00ca237f5cf135eda408 Mon Sep 17 00:00:00 2001 From: bjackson312006 Date: Tue, 26 May 2026 12:32:04 -0700 Subject: [PATCH 15/15] updated embedded-services to main --- platform/dev-mec/Cargo.lock | 32 ++++++++++++++++---------------- platform/dev-mec/Cargo.toml | 2 +- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/platform/dev-mec/Cargo.lock b/platform/dev-mec/Cargo.lock index 8277e1a..9d33d54 100644 --- a/platform/dev-mec/Cargo.lock +++ b/platform/dev-mec/Cargo.lock @@ -35,7 +35,7 @@ dependencies = [ [[package]] name = "battery-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "battery-service-interface", "defmt 0.3.100", @@ -51,7 +51,7 @@ dependencies = [ [[package]] name = "battery-service-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embedded-batteries-async", @@ -60,7 +60,7 @@ dependencies = [ [[package]] name = "battery-service-relay" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "battery-service-interface", "defmt 0.3.100", @@ -624,7 +624,7 @@ dependencies = [ [[package]] name = "embedded-services" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "bitfield 0.17.0", "cortex-m", @@ -779,9 +779,9 @@ checksum = "11d3d7f243d5c5a8b9bb5d6dd2b1602c0cb0b9db1621bafc7ed66e35ff9fe092" [[package]] name = "log" -version = "0.4.29" +version = "0.4.30" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5e5032e24019045c762d3c0f28f5b6b8bbf38563a65908389bf7978758920897" +checksum = "616ec5685824bcc94416c6d4a7a446eea774a31efd7062c8480ba6fd06d7a6e5" [[package]] name = "loom" @@ -808,7 +808,7 @@ dependencies = [ [[package]] name = "mctp-rs" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "bit-register 0.1.0 (git+https://github.com/OpenDevicePartnership/odp-utilities)", "defmt 0.3.100", @@ -893,7 +893,7 @@ dependencies = [ [[package]] name = "odp-service-common" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "embedded-services", "static_cell", @@ -968,7 +968,7 @@ checksum = "c33a9471896f1c69cecef8d20cbe2f7accd12527ce60845ff44c153bb2a21b49" [[package]] name = "power-policy-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "bitfield 0.17.0", "defmt 0.3.100", @@ -1184,7 +1184,7 @@ dependencies = [ [[package]] name = "thermal-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embassy-futures", @@ -1201,7 +1201,7 @@ dependencies = [ [[package]] name = "thermal-service-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embassy-time", @@ -1212,7 +1212,7 @@ dependencies = [ [[package]] name = "thermal-service-relay" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embedded-services", @@ -1253,7 +1253,7 @@ dependencies = [ [[package]] name = "time-alarm-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embassy-futures", @@ -1269,7 +1269,7 @@ dependencies = [ [[package]] name = "time-alarm-service-interface" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "bitfield 0.17.0", "defmt 0.3.100", @@ -1281,7 +1281,7 @@ dependencies = [ [[package]] name = "time-alarm-service-relay" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embedded-mcu-hal", @@ -1360,7 +1360,7 @@ checksum = "40ce102ab67701b8526c123c1bab5cbe42d7040ccfd0f64af1a385808d2f43de" [[package]] name = "uart-service" version = "0.1.0" -source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=v0.2.0#f1f1e087563085f853215ae24e7bc1290aa07168" +source = "git+https://github.com/OpenDevicePartnership/embedded-services?branch=main#5cc395f101ad574214a49b2894c484cc19d41695" dependencies = [ "defmt 0.3.100", "embassy-sync", diff --git a/platform/dev-mec/Cargo.toml b/platform/dev-mec/Cargo.toml index 2c8d0f2..b2be771 100644 --- a/platform/dev-mec/Cargo.toml +++ b/platform/dev-mec/Cargo.toml @@ -54,7 +54,7 @@ embassy-microchip = { git = "https://github.com/bjackson312006/embassy", branch "mec1723n_b0_sz", "rt", ] } -uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-services", branch = "v0.2.0", features = [ +uart-service = { git = "https://github.com/OpenDevicePartnership/embedded-services", branch = "main", features = [ "defmt", ] } static_cell = "2.1.0"